34AA04T-ESLASHST datasheet(10/36 Pages) MICROCHIP

10 / 36 page

34AA04

DS20005271B-page 10

 2014 Microchip Technology Inc.

6.0

WRITE OPERATIONS

6.1

Byte Write

Following the Start signal from the master, the control

code (4 bits), the Chip Select bits (3 bits) and the R/W

bit, which is a logic low, are placed onto the bus by the

master transmitter. This indicates to the addressed

slave receiver that the array address byte will follow,

once it has generated an Acknowledge bit during the

ninth clock cycle. Therefore, the next byte transmitted

by the master is the array address and will be written

into the Address Pointer of the 34AA04.

After receiving another Acknowledge signal from the

34AA04, the master device will transmit the data byte to

be written into the addressed memory location. The

34AA04 acknowledges again and the master generates

a Stop condition. This initiates the internal write cycle,

which means that during this time, the 34AA04 will not

generate Acknowledge signals (Figure 6-1).

If an attempt is made to write to a software write-pro-

tected portion of the array, the 34AA04 will not acknowl-

edge the data byte, no data will be written, and the

device will immediately accept a new command.

6.2

Page Write

The write control byte, array address and the first data

byte are transmitted to the 34AA04 in the same way as

in a byte write. Instead of generating a Stop condition,

the master transmits up to 15 additional data bytes to

the 34AA04, which are temporarily stored in the on-

chip page buffer and will be written into the memory

after the master has transmitted a Stop condition. Upon

receipt of each word, the four lower order Address

Pointer bits are internally incremented by one. The

higher order four bits of the array address, as well as

the bank selection, remain constant. If the master

should transmit more than 16 bytes prior to generating

the Stop condition, the address counter will roll over

and the previously received data will be overwritten. As

with the byte write operation, once the Stop condition is

received, an internal write cycle will begin (Figure 6-2).

If an attempt is made to write to a software write-pro-

tected portion of the array, the 34AA04 will not

acknowledge the data byte, no data will be written, and

the device will immediately accept a new command.

TABLE 6-1:

DEVICE RESPONSE WHEN WRITING DATA

FIGURE 6-1:

BYTE WRITE

Note:

It is recommended to perform a Set Bank

Address command before initiating a

Write command to ensure the desired

bank is selected.

Note:

When doing a write of less than 16 bytes,

the data in the rest of the page is

refreshed along with the data bytes being

written. This will force the entire page to

endure a write cycle. For this reason,

endurance is specified per page.

Note:

Page write operations are limited to

writing bytes within a single physical page,

regardless of the number of bytes actually

being written. Physical page boundaries

start at addresses that are integer multi-

ples of the page buffer size (or ‘page size’)

and end at addresses that are integer mul-

tiples of [page size – 1]. If a Page Write

command attempts to write across a phys-

ical page boundary, the result is that the

data wraps around to the beginning of the

current page (overwriting data previously

stored there), instead of being written to

the next page, as might be expected. It is,

therefore, necessary for the application

software to prevent page write operations

that would attempt to cross a page

boundary.

Status

Command

ACK

Address

ACK

Data Byte

ACK

Write Cycle

Protected with SWPn

Page or Byte Write in

Protected Block

ACK

Address

ACK

Data

NoACK

Not Protected

Page or Byte Write

ACK

Address

ACK

Data

ACK

Yes

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

Array

Address

Data

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