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DSC2133 DSC2233

Page 2

MK-Q-B-P-D-12050109

DSC2133

DSC2233

Pin Description

Pin No.

Pin Name

Pin Type

Description

1

Enable

I

Enables outputs when high and disables when low

2

NC

NA

Leave unconnected or grounded

3

NC

NA

DSC2133: Leave unconnected or grounded

SCLK

I

DSC2233: Serial clock from master

4

GND

Power

Ground

5

SDA

I

MOSI

DSC2233: SPI Serial Data from Master to Slave

6

SCL

I

MISO

O

DSC2233: SPI Serial Data from Slave to Master

7

CS_bar

I

SS

I

DSC2233: SPI Slave Select (Active Low)

8

Output1+

O

Positive LVDS Output 1

9

Output1-

O

Negative LVDS Output 1

10

Output 2-

O

Negative LVDS Output 2

11

Output 2+

O

Positive LVDS Output 2

12

VDD2

Power

Power Supply for LVDS Output 2

13

VDD

Power

Power Supply

14

FS

I

Default output clock frequency bit

Operational Description

The DSC2133/2233 is a dual LVDS oscillator

consisting of a MEMS resonator and a support

PLL IC. The outputs are generated through

independent 8-bit programmable dividers from

the output of the internal PLL.

DSC2133/2233 allows for easy programming

interface. Upon power-up, the initial output

frequencies are controlled by an internal pre-

programmed memory (OTP).

This memory

stores all coefficients required by the PLL for

two different default frequency pairs.

The

control pin (FS) selects the initial pair. Once

the device is powered up, a new output

frequency

pair

can

be

programmed.

Programming details are provided in the

Programming

Guide.

Standard

default

frequency pairs are described in the following

sections. Discera supports customer defined

versions of the DSC2133/2233.

When Enable (pin 1) is floated or connected to

VDD, the DSC2133/2233 is in operational

mode. Driving Enable to ground will tri-state

both output drivers (hi-impedance mode).