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LP2954, LP2954A

SNVS096E – JUNE 1999 – REVISED JULY 2016

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Copyright © 1999–2016, Texas Instruments Incorporated

(1)

At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heat sink values (if a

heat sink is used). If power dissipation causes the junction temperature to exceed specified limits, the device goes into thermal

shutdown.

(2)

If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1) (2)

MIN

MAX

UNIT

Input supply voltage

–20

30

V

Internally Limited

–65

150

°C

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE

UNIT

Electrostatic discharge

±2000

V

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

Operating junction temperature

–40

125

°C

(1)

For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2)

Conductivity Test Board for Leaded Surface Mount Packages.

(3)

The TO-220 (NDE) package is vertically mounted in center of JEDEC High-K test board (JESD 51-7) with no additional heat sink. This is

a through-hole package; this is NOT a surface mount package.

6.4 Thermal Information

LP2954, LP2954A

UNIT

KTT (DDPAK/TO-263)

NDE (TO-220)

D (SOIC)

3 PINS

3 PINS

8 PINS

(2)

Junction-to-ambient thermal resistance, High-K

44.3

105.0

°C/W

Junction-to-case (top) thermal resistance

44.8

38.6

47.3

°C/W

Junction-to-board thermal resistance

23.8

73.1

45.8

°C/W

Junction-to-top characterization parameter

10.6

13.5

6.2

°C/W

Junction-to-board characterization parameter

22.7

73.1

45.2

°C/W

Junction-to-case (bottom) thermal resistance

1.0

0.9

—

°C/W