LP3952RLSLASHNOPB datasheet(26/46 Pages) TI1

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SCL

SDA

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

LP3952

SNVS518A – JULY 2007 – REVISED MARCH 2013

www.ti.com

Table 5. Logic Interface Electrical Characteristics (1.65V

≤ VDDIO ≤ VDD1,2V) (unless otherwise noted)

Parameter

Test Conditions

Min

Typ

Max

Units

LOGIC INPUTS ADDR_SEL, NRST, SCL, PWM, SDA

VIL

Input Low Level

0.2×VDDIO

VIH

Input High Level

0.8×VDDIO

Logic Input Current

−1.0

1.0

μA

fSCL

Clock Frequency

400

kHz

LOGIC OUTPUT SDA

VOL

Output Low Level

ISDA = 3 mA

0.3

0.5

Output Leakage Current

VSDA = 2.8V

1.0

μA

Note: Any unused digital input pin has to be connected to GND to avoid floating and extra current consumption.

2C Compatible Interface

INTERFACE BUS OVERVIEW

The I2C compatible synchronous serial interface provides access to the programmable functions and registers on

the device. This protocol uses a two-wire interface for bi-directional communications between the devices

connected to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL).

These lines should be connected to a positive supply, via a pull-up resistor and remain HIGH even when the bus

is idle. Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending

on whether it generates or receives the serial clock (SCL).

DATA TRANSACTIONS

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock

(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the

SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New

data should be sent during the low SCL state. This protocol permits a single data line to transfer both

command/control information and data using the synchronous serial clock.

I2C DATA VALIDITY

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of

the data line can only be changed when CLK is LOW.

Figure 15. I2C Signals: Data Validity

I2C START AND STOP CONDITIONS

START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA

signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA

transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits.

The I2C bus is considered to be busy after START condition and free after STOP condition. During data

transmission, I2C master can generate repeated START conditions. First START and repeated START

conditions are equivalent, function-wise.

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