LP5550

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SNVS378G – OCTOBER 2005 – REVISED APRIL 2013

LP5550 PWI Register Map

The PWI standard supports sixteen 8-bit registers on the PWI slave. The table below summarizes these registers

and shows default register bit values after reset. The following sub-sections provide additional detail on the use

of each individual register.

Table 1. Summary

Register

Register

Reset Default Value

Register Usage

Type

Address

Name

7

6

5

4

3

2

1

0

0x0

R0

Core voltage

R/W

0

1

1

1

1

1

1

1

0x1

R1

Unused

R/W

-

-

-

-

-

-

-

-

0x2

R2

Memory retention voltage

R/W

0

1

1

0

0

-

-

-

0x3

R3

Status register

R/O

0

0

0

0

1

1

1

1

0x4

R4

PWI version number

R/O

0

0

0

0

0

0

0

1

0x5

R5

Unused

R/W

-

-

-

-

-

-

-

-

0x6

R6

Unused

R/W

-

-

-

-

-

-

-

-

0x7

R7

LDO2 voltage

R/W

0

1

1

1

1

-

-

-

0x8

R8

LDO1 voltage

R/W

0

0

1

0

1

-

-

-

0x9

R9

PFM/PWM force

R/W

0

0

-

-

-

-

-

-

0xA

R10

Unused

R/W

-

-

-

-

-

-

-

-

0xB

R11

Unused

R/W

-

-

-

-

-

-

-

-

0xC

R12

Unused

R/W

-

-

-

-

-

-

-

-

0xD

R13

Unused

R/W

-

-

-

-

-

-

-

-

0xE

R14

Unused

R/W

-

-

-

-

-

-

-

-

0xF

R15

Reserved

R/W

-

-

-

-

-

-

-

-

R0 - Core Voltage Register

Address 0x0

Type R/W

Reset Default 8h’7F

Bit

Field Name

Description or Comment

7

Sign

This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit

position using the Register Write command is ignored.

6:0

Voltage

Core voltage value. Default value is in bold.

Voltage Data Code [7:0]

Voltage Value (V)

7h’00

0.6

7h’xx

Linear scaling

7h’7f

1.2 (default)

R1 - Unused Register

Address 0x1

Type R/W

Reset Default 8h’00

Bit

Field Name

Description or Comment

7:0

Unused

Write transactions to this register are ignored. Read transactions will return a “No

Response Frame.” A no response frame contains all zeros (see PWI 1.0 specification).

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