TLK1201IRCPR datasheet(13/25 Pages) TI1

13 / 25 page

TLK1201RCP, TLK1201IRCP

ETHERNET TRANSCEIVERS

SLLS506E − AUGUST 2001 − REVISED MAY 2007

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

80%

50%

20%

80%

50%

20%

∼ V

80%

20%

0 V

∼ 1V

∼ −1V

TX+

TX−

VOD

Figure 7. Differential and Common-Mode

Output Voltage Definitions

5 pF

50 Ω

Figure 8. Transmitter Test Setup

LVTTL output switching characteristics over recommended operating conditions (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tr(RBC)

Clock rise time

0.3

1.5

tf(RBC)

Clock fall time

80% to 20% output voltage C 5 pF (see Figure 9)

0.3

1.5

Data rise time

80% to 20% output voltage, C = 5 pF (see Figure 9)

0.3

1.5

Data fall time

0.3

1.5

tsu(D1)

Data setup time (RD0..RD9), Data

valid prior to RBC0 rising

TBI normal mode, (see Figure 3)

2.5

th(D1)

Data hold time (RD0..RD9), Data valid

after RBC0 rising

TBI normal mode, (see Figure 3)

tsu(D2)

Data setup time (RD0..RD4)

DDR mode, Rω = 125 MHz, (see Figure 4)

th(D2)

Data hold time (RD0..RD4)

DDR mode, Rω = 125 MHz, (see Figure 4)

0.8

tsu(D3)

Data setup time (RD0..RD9)

TBI half-rate mode, Rω = 125 MHz, (see Figure 2)

2.5

th(D3)

Data hold time (RD0..RD9)

TBI half-rate mode, Rω = 125 MHz, (see Figure 2)

1.5

CLOCK

80%

50%

20%

2 V

0.8 V

DATA

1.4 V

Figure 9. TTL Data I/O Valid Levels for AC Measurement

transmitter timing requirements over recommended operating conditions (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tsu(D4)

Data setup time (TD0..TD9)

TBI modes

1.6

th(D4)

Data hold time (TD0..TD9)

TBI modes

0.8

tsu(D5)

Data setup time (TD0..TD9)

DDR modes

0.7

th(D5)

Data hold time (TD0..TD9)

DDR modes

0.5

tr, tf

TD[0,9] data rise and fall time

See Figure 9

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