TLV5618AMFKB datasheet(6/24 Pages) TI1

6 / 24 page

TLV5618A

2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT

DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS230H – JULY 1999 – REVISED JULY 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

digital input timing requirements

MIN

NOM

MAX

UNIT

C and I suffixes

VDD = 5 V

tsu(CS-CK)

Setup time, CS low before first negative SCLK edge

C and I suffixes

VDD = 3 V

tsu(CS-CK)

Setu time, CS low before first negative SCLK edge

Q and M suffixes

tsu(C16-CS)

Setup time, 16th negative SCLK edge before CS rising edge

tw(H)

SCLK pulse width high

tw(L)

SCLK pulse width low

C and I suffixes

VDD = 5 V

tsu(D)

Setup time, data ready before SCLK falling edge

C and I suffixes

VDD = 3 V

tsu(D)

Setu time, data ready before SCLK falling edge

Q and M suffixes

C and I suffixes

VDD = 5 V

th(D)

Hold time, data held valid after SCLK falling edge

C and I suffixes

VDD = 3 V

h(D)

Q and M suffixes

th(CSH)

Hold time CS high between cycles

VDD = 5 V

th(CSH)

Hold time, CS high between cycles

VDD = 3 V

timing requirements

tw(L)

SCLK

DIN

D15

D14

D13

D12

5 15

tw(H)

tsu(D) th(D)

tsu(CS-CK)

tsu(C16-CS)

Figure 1. Timing Diagram

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