(

) (

)

ISENSE

EAOUT

VINS

V

0.67

V

2.5 V

V

75mV

@

´

-

´

+

VDD

GDRV

GND

TZE

VSENSE

EAOUT

VINS

ISENSE

8

7

6

5

1

2

3

4

UCC28810

UCC28811

Table 1. PIN DESCRIPTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

Output of the transconductance error amplifier. The output current capability of this pin is 10

µA under normal

conditions, but increases to 1 mA when the voltage on VSENSE rises above 2.5 V. The EAOUT voltage is one of

the inputs to the current reference generator, with a dynamic input range of 2.5 V to 4.0 V. During zero energy or

EAOUT

2

O

overvoltage conditions, this pin goes below 2.5 V, nominal. When it goes below 2.3 V, the zero energy detect

comparator is activated which prevents the gate drive from switching. Loop compensation components are

connected between this pin and ground, or can be connected directly to the collector of the opto coupler in isolated

applications.

The device reference ground. All bypassing elements are connected to the GND pin with the shortest traces

GND

6

–

possible.

The gate drive output driving the flyback, buck, or boost switch. This output is capable of delivering up to 750-mA

GDRV

7

O

peak currents during turn-on and turn-off. An external gate drive resistor may be needed to limit the peak current

depending upon the VDD voltage being used. Below the UVLO threshold, the output is held low.

This pin senses the instantaneous switch current in the external switch and uses this signal as the internal ramp for

the current sense comparator. A small internal noise filter is provided. If additional filtering is needed, an external

R-C filter may be added to further suppress noise spikes. An internal clamp on the current reference generator

ISENSE

4

I

to limit the zero crossing distortion. The ISENSE threshold voltage is approximately equal to:

This pin is the input for the transformer zero energy detect comparator. A bias winding can be used to sense the

transformer zero energy. The transition is detected when the inductor current falls to zero and the TZE input goes

TZE

5

I

low. Internal active clamps are provided to prevent TZE from going below ground or rising too high. If zero energy is

not detected within 400

µs, a restart timer sets the latch and the gate drive high.

The supply voltage for the device. This pin must be bypassed with a high-frequency capacitor (not less than 0.1

µF)

and tied directly to GND with the shortest traces possible. The UCC28810 has a wide UVLO hysteresis, typically

6.3 V, which allows use of a lower value holdup capacitor on VDD, resulting in faster start up. The UCC28811 has a

VDD

8

I

narrow UVLO hysteresis, typically 2.8 V, and a typical turn-on threshold of 12.5 V for applications where the device

needs to be controlled by a downstream PWM controller. This narrower UVLO hysteresis requires a larger value

holdup capacitor.

This pin senses the instantaneous regulator input voltage through an external voltage divider. The VINS voltage

VINS

3

I

acts as one of the inputs to the current reference generator. The recommended operating range is 0 V to 3.8 V at

high line.

This pin is the inverting input to the transconductance amplifier, with a nominal value of 2.5 V, and is also the input

to the OVP comparator. Pulling this pin below the ENABLE threshold turns off the output switching, providing the

VSENSE

1

I

ability to externally disable the converter. This function also provides feedback fault protection, ensuring no runaway

if the feedback path is open. When using the internal error amplifier, this pin senses the output voltage through a

voltage divider.

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