CY7C68310
Document 38-08030 Rev. *H
Page 27 of 34
7.0
Timing Characteristics
7.1
I2C-compatible Memory Device Interface Timing
7.2
USB Interface Timing
The CY7C68310 transceiver complies to the timing character-
istics as stated in the USB Specification version 2.0. The
CY7C68310 can operate at either the high-speed or full-speed
signalling rate.
7.3
ATA/ATAPI Interface Timing
The ATA interface supports ATA PIO modes 0 to 4, and Ultra
DMA modes 0 to 4, per the ATA Attachment – 6 with Packet
Interface revision 3b. All input signals on the ATA/ATAPI port
are considered asynchronous and are synchronized to the
chip's internal system clock. All output signals are clocked
using the chip’s internal system clock, for which there is no
external reference. Thus, the output signals should also be
considered asynchronous. The PIO mode used for data
register accesses is retrieved from the device or specified in
the CY7C68310 configuration bytes.
7.4
External Clock Source Timing
The CY7C68310 derives its internal system clock from an
external clock source. The external clock input signal
frequency is measured at one half of the 2.5V power source
(VDD25). The CY7C68310 internal PLL can be clocked using
either a 30-MHz (±0.005%) fundamental-mode crystal or a
2.5V, 50% duty-cycle square wave. The recommended
external clock source for the CY7C68310 is the PRE
XH30PRF10BL crystal (10-pF load capacitance).
7.5
Reset Timing
The CY7C68310 requires an off-chip power-on reset circuit.
nRESET must be held asserted for a minimum of 1 ms after
power is stable to cause a chip reset.
8.0
External Circuitry Requirements
Certain
external
components
are
required
for
proper
CY7C68310 operation. The following figure details the
minimum required circuitry for normal operation. Additional
components may be required to support configurable
CY7C68310 features, if utilized.
I2C-compatible Device Parameter
Symbol
Value
Clock high time
Thigh
5066 ns
Clock low time
Tlow
5066 ns
Start condition hold time
THD:STA
5066 ns
Start condition set-up time
TSU:STA
5066 ns
Data output hold time
THD:DAT
5066 ns
Data output set-up time
TSU:DAT
5066 ns
Stop condition set-up time
TSU:STO
5066 ns
Required data valid before clock
TDSU
500 ns
Min time bus must be free before next transmission
TBUF
5066 ns
Figure 7-1. I2C Interface Timing
T
low
T
high
T
HD:STA
T
SU:STA
T
HD:DAT
T
SU:DAT
T
DSU
SCL
SDA OUT
SDA IN
T
BUF
T
SU:STO
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