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DS3883 Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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DS3883 Datasheet(HTML) 4 Page - National Semiconductor (TI) |
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4 / 9 page ![]() DC Electrical Characteristics (Notes 2, 3) (Continued) Note 1: “Absolute Maximum Ratings” are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 2: All input and/or output pins shall not exceed VCC + 0.5V and shall not exceed the absolute maximum rating at any time, including power-up and power-down. This prevents the ESD structure from being damaged due to excessive currents flowing from the input and/or output pins to QV CC and VCC. There is a diode between each input and/or output to VCC which is forward biased when incorrect sequencing is applied. LI and Bn pins do not have power sequencing requirements with re- spect to V CC and QVCC. Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. All typical values are specified under these conditions: VCC = 5V and TA = 25˚C, unless otherwise stated. Note 4: Only one output should be shorted at a time, and duration of the short should not exceed one second. Note 5: Referenced to appropriate signal ground. Do not exceed maximum power dissipation of package. AC Electrical Characteristics (Note 6) T A = 0˚C to +70˚C, VCC = 5V ±10% Symbol Parameter Conditions Min Typ Max Units DRIVER t PHL An to Bn Propagation Delay CD = 0V, T/ R = 3V 1 3.5 6 ns t PLH ( Figure 1 and Figure 2) 1 3.5 6 ns t PHL CD to Bn Enable Time T/R = An = 3V 369 ns t PLH Disable Time ( Figure 1 and Figure 3 ) 2.5 5 8 ns t PHL T/R to Bn Enable Time ( Figure 8 and Figure 9) 9 13.5 18 ns t PLH Disable Time CD = 0V 2 6 10 ns t r Transition Time — Rise/Fall ( Figure 1 and Figure 2) 1 2.5 4.5 ns t f 20% to 80% CD = 0V, T/R = 3V (Note 10) 1 2 4.5 ns SR Slew Rate is Calculated ( Figure 1 and Figure 2) (Note 10) 0.5 V/ns from 1.3V to 1.8V CD = 0V T/R = 3V t SKEW An to Bn Skew (Same Package) (Note 7) 1 3.5 ns RECEIVER t PHL Bn to An CD = T/ R = 0V 247 ns t PLH ( Figure 4 and Figure 5 ) 1.5 4.5 7.5 ns t PLZ CD to An Disable Time Bn = 2.1V, T/R = 0V 4 8 12 ns t PZL Enable Time ( Figure 6 and Figure 7 ) 2.5 6 9 ns t PHZ Disable Time Bn = 1.1V, T/R = 0V 3 6.5 10 ns t PZH Enable Time ( Figure 6 and Figure 7 )2 6 10 ns t PLZ T/R to An Disable Time CD = 0V Bn = 2.1V 3 7 12 ns t PZL Enable Time ( Figure 8 and Figure 9 ) 4 10 16 ns t PHZ Disable Time Bn = 1.1V, CD = 0V 2 6.5 10 ns t PZH Enable Time ( Figure 6 and Figure 7 )3 7 11 ns t SKEW Bn to An Skew (Same Package) (Note 7) 1 3.5 ns PARAMETERS NOT TESTED C output BTL Output Capacitance (Note 8) 5 pF t NR Noise Rejection (Note 9) 1 ns Note 6: Input waveforms shall have a rise/fall time of 3 ns. Propagation delays are measured with a single output switching. Note 7: tSKEW is an absolute value defined as differences seen in propagation delays between drivers in the same package with identical load conditions. Note 8: The parameter is tested using TDR techniques described in 1194.0 BTL backplane Design Guide. Note 9: This parameter is tested during device characterization. The measurement revealed that the part will reject 1 ns pulse widths. Note 10: Futurebus+ transceivers are required to limit bus signal rise and fall times to no faster than 0.5 V/ns, measured between 1.3V and 1.8V (approximately 20% to 80% of nominal voltage swing). The rise and fall times are measured with a transceiver loading equivalent to 12.5 Ω tied to +2.1V DC. www.national.com 4 |
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