TLV2556

SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002

21

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PARAMETER MEASUREMENT INFORMATION

VOH

VOL

VOH

VOL

VIL

VIH

Last

Clock

tconv

td4

tt3

tt3

I/O CLOCK

EOC

INT

VOH

VOL

VOH

VOL

tt3

tt3

VOH

VOL

MSB

Valid

EOC

INT

DATA

OUT

Figure 41. I/O CLOCK and EOC Voltage

Waveforms

Figure 42. EOC and DATA OUT Voltage

Waveforms

td6

td7

Figure 43. CS and EOC Voltage Waveforms

Figure 44. I/O CLOCK and EOC Voltage

Waveforms

th5

th6

th7

td9

VIL

VOL

VOH

CS

EOC

INT

VOH

VOL

VOH

VIL

I/O CLOCK

EOC

INT

timing information

DATA OUT

1

2

3

5

4

610

11

12

1

I/O CLOCK

Hi–Z State

DATA IN

8

7

9

D7

16

D3

D2

D1

D0

Configure CFGR1

1st Conversion Cycle

CS

First Cycle After Power-Up: Configure CFGR2

Access Cycle

Data Cycle

Invalid Conversion Data

Command 1111

CFGR2 Data

NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to

control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.

Figure 45. Timing for CFGR2 Configuration

The host must configure CFGR2 before valid device conversions can begin. This can be accessed through

command 1111. This can be done using eight, twelve, or sixteen I/O CLOCK clocks. (A minimum of eight is

required to fully program CFGR2.)

After CFGR2 is configured, the following cycle configures CFGR1 and a valid sample/conversion is performed.

CS can be held low for each remaining cycle. First valid conversion output data is available on the third cycle

after power up.