CY2071A
Document #: 38-07139 Rev. *A
Page 3 of 8
Operating Conditions[3]
Parameter
Description
Min.
Max.
Unit
VDD
Supply Voltage, 5.0V Operation
4.5
5.5
V
VDD
Supply Voltage, 3.3V Operation
3.0
3.6
V
TA
Commercial Operating Temperature, Ambient
0
70
°C
Industrial Operating Temperature, Ambient
–40
85
°C
CL
Max. Load Capacitance per Output (5V Operation)
25
pF
Max. Load Capacitance per Output (3.3V Operation)
15
pF
fREF
External Reference Crystal
10.0
25.0
MHz
External Reference Clock[4, 5]
1.0
30.0
MHz
tPU
Power-up time for all VDD's to reach minimum specified voltage (power
ramps must be monotonic)
0.05
50
ms
Electrical Characteristics, Commercial 5.0V VDD = 5V ±10%, TA = 0°C to +70°C
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
VOH
HIGH-Level Output Voltage
IOH = –4.0 mA
2.4
V
VOL
LOW-Level Output Voltage
IOL = 4.0 mA
0.4
V
VIH
HIGH-Level Input Voltage[6]
Except Crystal Pins
2.0
V
VIL
LOW-Level Output Voltage[6]
Except Crystal Pins
0.8
V
IIH
Input HIGH Current
VIN = VDD – 0.5V
10
µA
IIL
Input LOW Current
VIN = 0.5V
150
µA
IOZ
Output Leakage Current
Three State Outputs
250
µA
IDD
VDD Supply Current
[7]
VDD = VDD max. 5V operation, CL = 25 pF
40
60
mA
Electrical Characteristics, Commercial 3.3V VDD = 3.3V ±10%, TA = 0°C to +70°C
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
VOH
HIGH-Level Output Voltage
IOH = –4.0 mA
2.4
V
VOL
LOW-Level Output Voltage
IOL = 4.0 mA
0.4
V
VIH
HIGH-Level Input Voltage[6]
Except Crystal Pins
2.0
V
VIL
LOW-Level Output Voltage[6]
Except Crystal Pins
0.8
V
IIH
Input HIGH Current
VIN = VDD – 0.5V
10
µA
IIL
Input LOW Current
VIN = 0.5V
150
µA
IOZ
Output Leakage Current
Three State Outputs
250
µA
IDD
VDD Supply Current
[7]
VDD = VDD max. 3.3V operation, CL = 15 pF
24
40
mA
Notes:
3.
Electrical parameters are guaranteed with these operating conditions. Values for 3.3V operation are shown in parentheses.
4.
External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2.
5.
Please refer to application note “Crystal Oscillator Topics” for information on AC-coupling the external input reference clock.
6.
Xtal inputs have CMOS thresholds.
7.
Load = max, typical configuration, fREF = 14.318 MHz. Specific configurations may vary. A close approximation of IDD can be derived by the following formula:
IDD(mA) = VDD*(6.25+(0.055*FREF) + (0.0017*CLOAD*(FCLKA+FCLKB+FCLKC))). CLOAD is specified in pF and F is specified in MHz.
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