®

OPA621

13

OPA621

0 to –2V

V

OUT

To Active Probe (Channel 2)

on sampling scope.

200

Ω

100

Ω

V

IN

0 to +2V, f = 1.25MHz

+5VDC

–5VDC

1pF to 4pF (Adjust for Optimum Settling)

200

Ω

NOTE: Test fixture built using all surface-mount components. Ground

plane used on component side and entire fixture enclosed in metal case.

Both power supplies bypassed with 10

µF Tantalum || 0.01µF ceramic

capacitors. It is directly connected (without cable) to TIME CAL trigger

source on Sampling Scope (Data Precision's Data 6100 with Model

640-1 plug-in). Input monitored with Active Probe (Channel 1).

FIGURE 7. Settling Time Test Circuit.

error band of

±200µV centered around the final value of 2V.

Settling time, specified in an inverting gain of two, occurs in

only 25ns to 0.01% for a 2V step, making the OPA621 one

of the fastest settling monolithic amplifiers commercially

available. Settling time increases with closed-loop gain and

output voltage change as described in the Typical Perform-

ance Curves. Preserving settling time requires critical

attention to the details as mentioned under “Wiring Precau-

tions.” The amplifier also recovers quickly from input

overloads. Overload recovery time to linear operation from

a 50% overload is typically only 30ns.

In practice, settling time measurements on the OPA621

prove to be very difficult to perform. Accurate measurement

is next to impossible in all but the very best equipped labs.

Among other things, a fast flat-top generator and high speed

oscilloscope are needed. Unfortunately, fast flat-top genera-

tors, which settle to 0.01% in sufficient time, are scarce and

expensive. Fast oscilloscopes, however, are more commonly

available. For best results a sampling oscilloscope is recom-

mended. Sampling scopes typically have bandwidths that

are greater than 1GHz and very low capacitance inputs.

They also exhibit faster settling times in response to signals

that would tend to overload a real-time oscilloscope.

Figure 7 shows the test circuit used to measure settling time

for the OPA621. This approach uses a 16-bit sampling

oscilloscope to monitor the input and output pulses. These

waveforms are captured by the sampling scope, averaged,

and then subtracted from each other in software to produce

the error signal. This technique eliminates the need for the

traditional “false-summing junction,” which adds extra

parasitic capacitance. Note that instead of an additional flat-

top generator, this technique uses the scope’s built-in cali-

bration source as the input signal.

DIFFERENTIAL GAIN AND PHASE

Differential Gain (DG) and Differential Phase (DP) are

among the more important specifications for video applica-

tions. DG is defined as the percent change in closed-loop

gain over a specified change in output voltage level. DP is

COMPENSATION

The OPA621 is stable in inverting gains of

≥–2V/V and in

non-inverting gains

≥+2V/V. Phase margin for both con-

figurations is approximately 50

°. Inverting and non-invert-

ing gains of unity should be avoided. The minimum stable

gains of +2V/V and –2V/V are the most demanding circuit

configurations for loop stability and oscillations are most

likely to occur in these gains. If possible, use the device in

a noise gain greater than three to improve phase margin and

reduce the susceptibility to oscillation. (Note that, from a

stability standpoint, an inverting gain of –2V/V is equivalent

to a noise gain of 3.) Gain and phase response for other gains

are shown in the Typical Performance Curves.

The high-frequency response of the OPA621 in a good

layout is flat with frequency for higher-gain circuits. How-

ever, low-gain circuits and configurations where large

feedback resistances are used, can produce high-frequency

gain peaking. This peaking can be minimized by connecting

a small capacitor in parallel with the feedback resistor. This

capacitor compensates for the closed-loop, high frequency,

transfer function zero that results from the time constant

formed by the input capacitance of the amplifier (typically

2pF after PC board mounting), and the input and feedback

resistors. The selected compensation capacitor may be a

trimmer, a fixed capacitor, or a planned PC board capaci-

tance. The capacitance value is strongly dependent on circuit

layout and closed-loop gain. Using small resistor values will

preserve the phase margin and avoid peaking by keeping the

break frequency of this zero sufficiently high. When high

closed-loop gains are required, a three-resistor attenuator

(tee network) is recommended to avoid using large value

resistors with large time constants.

SETTLING TIME

Settling time is defined as the total time required, from the

input signal step, for the output to settle to within the

specified error band around the final value. This error band

is expressed as a percentage of the value of the output

transition, a 2V step. Thus, settling time to 0.01% requires an