BQ26221 datasheet(13/20 Pages) TI

13 / 20 page

bq26221

SLUS607 − MAY 2004

www.ti.com

APPLICATION INFORMATION

single-byte programming

To program an individual byte in flash, the byte of data is first written into the FPD register while the address

to be programmed is written into the FPA register. The program byte command, 0x0F, is then written to the

FCMD. The result of this sequence is that the contents of the FPD register is logically ANDed with the contents

of the flash address pointed to by the FPA register.

RAM-to-flash transfer

The content of the flash that shadows the user RAM is logically ANDed to the RAM contents when the

RAM-to-flash transfer command is sent. If new data is to be written over old data, then it is necessary to first

erase the flash page that is being updated and restore all necessary data.

communicating with the bq26221

The bq26221 includes a single-wire HDQ serial data interface. Host processors, configured for either polled or

interrupt processing, use the interface to access various bq26221 registers. The HDQ pin requires an external

pull-up resistor. The interface uses a command-based protocol, where the host processor sends a command

byte to the bq26221. The command directs the bq26221 either to store the next eight bits of data received to

a register specified by the command byte, or, to output the eight bits of data from a register specified by the

command byte.

The communication protocol is asynchronous return-to-one and is referenced to VSS. Command and data

bytes consist of a stream of eight bits that have a maximum transmission rate of 5 Kbits/s. The least-significant

bit of a command or data byte is transmitted first. Data input from the bq26221 may be sampled using the

pulse-width capture timers available on some microcontrollers. A UART, (universal asynchronous receiver

transmitter), also communicates with the bq26221.

If a communication time out occurs (for example, if the host waits longer than t(CYCB) for the bq26221 to respond

or if this is the first access command), then a BREAK should be sent by the host. The host may then resend

the command. The bq26221 detects a BREAK when the HDQ pin is driven to a logic-low state for a time t(B)

or greater. The HDQ pin then returns to its normal ready-high logic state for a time t(BR).The bq26221 is then

ready for a command from the host processor.

The return-to-one data-bit frame consists of three distinct sections:

The first section starts the transmission by either the host or the bq26221 taking the HDQ pin to a logic-low

state for a period equal to t(HW1) or t(DW1).

The next section is the actual data transmission, where the data should be valid by a period equal to t(HW1)

or t(DW1), after the negative edge that starts communication. The data should be held for t(HW0) and t(DW0)

periods to allow the host or bq26221 to sample the data bit.

The final section stops the transmission by returning the HDQ pin to a logic-high state by at least a period

equal to t(DW0) or t(HW0) after the negative edge used to start communication. The final logic-high state

should be held until a period equal to t(CYCH) or t(CYCB), to allow time to ensure that the bit transmission

ceased properly.

BQ26221 Datasheet(PDF) 13 Page - Texas Instruments