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GS1672 Datasheet(PDF) 13 Page - Semtech Corporation

Part # GS1672
Description  HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support
PDF  116 Pages
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Manufacturer  SEMTECH [Semtech Corporation]
Direct Link  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

GS1672 Datasheet(HTML) 13 Page - Semtech Corporation

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GS1672 HD/SD-SDI Serializer with Complete SMPTE
Audio & Video Support
Data Sheet
53623 - 6
July 2011
13 of 116
E7
TDI
Input
COMMUNICATION SIGNAL INPUT.
Signal levels are LVCMOS/LVTTL compatible.
Dedicated JTAG pin.
Test data in.
This pin is used to shift JTAG test data into the device when the
JTAG/HOST pin is LOW.
E8
TMS
Input
COMMUNICATION SIGNAL INPUT.
Signal levels are LVCMOS/LVTTL compatible.
Dedicated JTAG pin.
Test mode start.
This pin is JTAG Test Mode Start, used to control the operation of
the JTAG test when the JTAG/HOST pin is LOW.
E10
CD_VDD
Input Power
Power for the serial digital cable driver. Connect to 3.3V DC analog.
F1, F2, H1,
H2, J1, J2,
J3, K1, K2,
K3
DIN[9:0]
Input
PARALLEL DATA BUS.
Signal levels are LVCMOS / LVTTL compatible.
In 10-bit mode, these pins are not used.
20-bit mode
20BIT/10BIT = HIGH
Chroma data input in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data input in data through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
Not Used in DVB-ASI mode
SMPTE_BYPASS = LOW
DVB_ASI = HIGH
10-bit mode
20BIT/10BIT = LOW
High impedance.
F3
DETECT_TRS
Input
CONTROL SIGNAL INPUT.
Signal levels are LVCMOS / LVTTL compatible.
Used to select external HVF timing mode or TRS extraction timing
mode.
When DETECT_TRS is LOW, the device extracts all internal timing
from the supplied H:V:F or CEA-861 timing signals, dependent on
the status of the TIM861 pin.
When DETECT_TRS is HIGH, the device extracts all internal timing
from TRS signals embedded in the supplied video stream.
F8
TDO
Output
COMMUNICATION SIGNAL OUTPUT.
Signal levels are LVCMOS/LVTTL compatible.
Dedicated JTAG pin.
JTAG Test Data Output.
This pin is used to shift results from the device when the JTAG/HOST
pin is LOW.
F10
RSET
Input
An external 1% resistor connected to this input is used to set the
SDO/SDO output signal amplitude.
G1, H10
IO_VDD
Input Power
Power connection for digital I/O. Connect to 3.3V or 1.8V DC digital.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description



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