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Revision 1.07

ACB Control Status Register (ACBnCST)

The ACBnCST register maintains current ACB status and controls several ACB module functions, as described below. On

reset and when the module is disabled, the non-reserved bits of ACBnCST are cleared (0016).

Location: Channel 1 - 00 FF6416

Channel 2 - 00 FFE416

Type: Varies per bit

Bit

76543210

Name

ARPMATCH MATCHAF

TGSCL

TSDA

GCMATCH

MATCH

BUSY

Reset

00000000

Bit

Type

Description

0RO

BUSY. When set (1), indicates that the ACB module is in one of the following states:

–

Generating a Start Condition

–

In Master mode (MASTER in ACBnST register is set)

–

In Slave mode (MATCH or GMATCH in ACBnCST register is set)

–

In the period between detecting a Start Condition and completing the reception of the address byte;

after this, the ACB either becomes not busy or enters Slave mode.

The BUSY bit is cleared by the completion of any of the above states or by disabling the module. It

should always be written 0.

R/W1C BB (Bus Busy). When set (1), indicates the bus is busy. It is set either when the bus is active (i.e., a

low level on either SDA or SCL) or by a Start Condition. It is cleared when the module is disabled, on

detection of a Stop Condition or by writing 1 to this bit. See Section 4.13.9 on page 207 for a

description of the use of this bit.

2RO

MATCH (Address Match). In Slave mode, MATCH is set (1) when SAEN in ACBnADDR register is

set and the first seven bits of the address byte (the first byte transferred after a Start Condition) match

the 7-bit address in ACBnADDR register. It is cleared by Start Condition, a Repeated Start or a Stop

Condition (including illegal Start or Stop Condition).

3RO

GCMATCH (Global Call Match). In Slave mode, GCMTCH is set (1) when GCMEN in ACBnCTL1

cleared by a Start Condition, a Repeated Start or a Stop Condition (including illegal Start or Stop

Condition).

4RO

TSDA (Test SDA Line). Reads the current value of the SDA line. This bit can be used while

recovering from an error condition in which the SDA line is constantly pulled low by a slave that went

out of synch. Data written to this bit is ignored.

R/W

TGSCL (Toggle SCL Line). Enables toggling the SCL line during the process of error recovery. When

the SDA line is low, writing 1 to this bit toggles the SCL line for one cycle. Writing 1 to TGSCL while

SDA is high is ignored. The bit is cleared when the clock toggle is completed.

6RO

MATCHAF (Match Address Field). When the MATCH bit is set, MATCHAF indicates with which of

the two possible slave addresses (ADDR cleared in ACBnADDR register or set in ACBnADDR2

7RO

ARPMATCH (ARP address Match). In Slave mode, ARPMTCH is set (1) when ARPMEN in

ACBnCTL3 register is set and the address byte (the ﬁrst byte transferred after a Start Condition) is

110 00012. It is cleared by Start Condition, a Repeated Start or a Stop Condition (including illegal Start

or Stop Condition).

PC87591L Datasheet(PDF) 204 Page - National Semiconductor (TI)

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