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CY7C343
Document #: 38-03015 Rev. *B
Page 7 of 19
tPR
Asynchronous Preset Recovery Time[5, 8]
Com’l/Ind
20
25
ns
Mil
20
25
tPO
Asynchronous Preset to Registered Output Delay[8]
Com’l/Ind
20
25
ns
Mil
20
25
tCF
Synchronous Clock to Local Feedback Input[5, 14]
Com’l/Ind
3
3
ns
Mil
3
3
tP
External Synchronous Clock Period (1/fMAX3)
[5]
Com’l/Ind
12
16
ns
Mil
12
16
fMAX1
External Maximum Frequency (1/(tCO1 + tS1))
[5, 15]
Com’l/Ind
41.6
34
MHz
Mil
41.6
34
fMAX2
Internal Local Feedback Maximum Frequency, lesser of (1/(tS1
+ tCF)) or (1/tCO1)
[5, 16]
Com’l/Ind
66.6
55
MHz
Mil
66.6
55
fMAX3
Data Path Maximum Frequency, least of 1/(tWL + tWH), 1/(tS1 + tH),
or (1/tCO1)
[5, 17]
Com’l/Ind
83.3
62.5
MHz
Mil
83.3
62.5
fMAX4
Maximum Register Toggle Frequency (1/(tWL+tWH))
[5, 18]
Com’l/Ind
83.3
62.5
MHz
Mil
83.3
62.5
tOH
Output Data Stable Time from Synchronous Clock Input[5, 19]
Com’l/Ind
3
3
ns
Mil
3
3
tPW
Asynchronous Preset Width[5, 8]
Com’l/Ind
20
25
ns
Mil
20
25
Notes:
14. This specification is a measure of the delay associated with the internal register feedback path. This is the delay from synchronous clock to LAB logic array input.
This delay plus the register set-up time, tS1, is the minimum internal period for an internal synchronous state machine configuration. This delay is for feedback within the same
LAB. This parameter is tested periodically by sampling production material.
15. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration with external feedback can operate.
It is assumed that all data inputs and feedback signals are applied to dedicated inputs.
16. This specification indicates the guaranteed maximum frequency at which a state machine, with internal-only feedback, can operate. If register output states must
also control external points, this frequency can still be observed as long as this frequency is less than 1/tCO1. All feedback is assumed to be local, originating within
the same LAB..
17. This frequency indicates the maximum frequency at which the device may operate in data path mode. This delay assumes data input signals are applied to
dedicated inputs and no expander logic is used.
18. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycled.
19. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.
External Synchronous Switching Characteristics Over Operating Range (continued)[7]
Parameter
Description
7C343-20
7C343-25
Unit
Min.
Max.
Min.
Max.
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