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CY7C68000
PRELIMINARY
Document #: 38-08016 Rev. *E
Page 3 of 14
5.0
Pin Assignments
The following pages illustrate the individual pin diagrams that
are available in the 56-pin QFN and 56-pin SSOP packages.
The packages offered use either an 8-bit (60-MHz) or 16-bit
(30-MHz) bus interface.
56-pin QFN
Figure 5-1. CY7C68000 56-pin QFN Pin Assignment
1
2
3
4
5
6
7
8
9
10
11
12
13
14
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
D5
Reserved
D6
D7
D8
D9
Reserved
D10
D11
VCC
D12
GND
D13
TXReady
Suspend
Reset
AVCC
XTALOUT
XTALIN
AGND
AVCC
DPLUS
DMINUS
AGND
XcvrSelect
TermSelect
OpMode0
CY7C68000
56-pin QFN