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CY2280
Document #: 38-07207 Rev. *A
Page 5 of 12
Notes:
4.
Electrical parameters are guaranteed with these operating conditions.
5.
Crystal Inputs have CMOS thresholds.
6.
Parameter is guaranteed by design and characterization. Not 100% tested in production.
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min. Max. Unit
Switching Characteristics[6, 7]
Parameter
Output
Description
Test Conditions
Min.
Typ.
Max.
Unit
t1
All
Output Duty Cycle[8]
t1 = t1A ÷ t1B
45
50
55
%
t2
CPUCLK,
APIC
CPU and APIC Clock
Rising and Falling Edge
Rate
Between 0.4V and 2.0V
-1,-11S,
-21S
1.0
4.0
V/ns
t2
PCICLK
PCI Clock Rising and
Falling Edge Rate
Between 0.4V and 2.4V
-1,-11S,
-21S
1.0
4.0
V/ns
t2
USBCLK,
REF
USB, REF Rising and
Falling Edge Rate
Between 0.4V and 2.4V
0.5
2.0
V/ns
t3
CPUCLK
CPU Clock Rise Time
Between 0.4V and 2.0V
-1,-11S,
-21S
0.4
1.6
ns
t4
CPUCLK
CPU Clock Fall Time
Between 2.0V and 0.4V
-1,-11S,
-21S
0.4
1.6
ns
t5
CPUCLK
CPU-CPU Clock Skew
Measured at 1.25V
100
175
ps
t6
CPUCLK,
PCICLK
CPU-PCI Clock Skew[9]
Measured at 1.25V for 2.5V
clocks, and at 1.5V for 3.3V
clocks
-1,-11S,
-21S
1.5
4.0
ns
t7
PCICLK,
PCICLK
PCI-PCI Clock Skew
Measured at 1.5V
250
ps
t8
CPUCLK,
APIC
CPU-APIC Clock
Skew[10]
Measured at 1.25V for 2.5V
clocks
-21S
2.0
4.5
ns
t9
APIC
APIC-APIC Clock Skew
Measured at 1.25V
100
175
ps
t10
CPUCLK
Cycle-Cycle Clock Jitter
Measured at 1.25V
-1,-11S,
-21S
200
250
ps
t11
PCICLK
Cycle-Cycle Clock Jitter
Measured at 1.5V
250
500
ps
t12
CPUCLK,
PCICLK
Power-up Time
CPU, PCI clock stabilization from
power-up
3
ms
Notes:
7.
All parameters specified with loaded outputs.
8.
Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V.
9.
PCI lags CPU for -11S and -21S options.
10. APIC lags CPU for -21S option.
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