Rev: 1.12 7/2002

12/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS84018/32/36AT/B-180/166/150/100

Synchronous Truth Table

Operation

Address

Used

State

Diagram

ADSP ADSC

ADV

Deselect Cycle, Power Down

None

X

H

X

X

L

X

X

High-Z

Deselect Cycle, Power Down

None

X

L

F

L

X

X

X

High-Z

Deselect Cycle, Power Down

None

X

L

F

H

L

X

X

High-Z

Read Cycle, Begin Burst

External

R

L

T

L

X

X

X

Q

Read Cycle, Begin Burst

External

R

L

T

H

L

X

F

Q

Write Cycle, Begin Burst

External

W

L

T

H

L

X

T

D

Read Cycle, Continue Burst

Next

CR

X

X

H

H

L

F

Q

Read Cycle, Continue Burst

Next

CR

H

X

X

H

L

F

Q

Write Cycle, Continue Burst

Next

CW

X

X

H

H

L

T

D

Write Cycle, Continue Burst

Next

CW

H

X

X

H

L

T

D

Read Cycle, Suspend Burst

Current

X

X

H

H

H

F

Q

Read Cycle, Suspend Burst

Current

H

X

X

H

H

F

Q

Write Cycle, Suspend Burst

Current

X

X

H

H

H

T

D

Write Cycle, Suspend Burst

Current

H

X

X

H

H

T

D

Notes:

1. X = Don’t Care, H = High, L = Low.

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as “Q” in the Truth Table above).

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.