PCI1520 datasheet(51/138 Pages) TI

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3−15

Table 3−8. PCI1520 Registers Used to Program Serial-Bus Devices

PCI OFFSET

DESCRIPTION

B0h

Serial-bus data

Contains the data byte to send on write commands or the received data byte on read commands.

B1h

Serial-bus index

The content of this register is sent as the word address on byte writes or reads. This register is not used

in the quick command protocol.

B2h

Serial-bus slave

address

Write transactions to this register initiate a serial-bus transaction. The slave device address and the

R/W command selector are programmed through this register.

B3h

Serial-bus control

and status

Read data valid, general busy, and general error status are communicated through this register. In

addition, the protocol-select bit is programmed through this register.

3.7

Programmable Interrupt Subsystem

Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic

nature of PC Cards and the abundance of PC Card I/O applications require substantial interrupt support from the

PCI1520. The PCI1520 provides several interrupt signaling schemes to accommodate the needs of a variety of

platforms. The different mechanisms for dealing with interrupts in this device are based on various specifications and

industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the

CardBus socket register set provides interrupt control for the CardBus PC Card functions. The PCI1520 is, therefore,

backward compatible with existing interrupt control register definitions, and new registers have been defined where

required.

The PCI1520 detects PC Card interrupts and events at the PC Card interface and notifies the host controller using

one of several interrupt signaling protocols. To simplify the discussion of interrupts in the PCI1520, PC Card interrupts

are classified either as card status change (CSC) or as functional interrupts.

The method by which any type of PCI1520 interrupt is communicated to the host interrupt controller varies from

system to system. The PCI1520 offers system designers the choice of using parallel PCI interrupt signaling, parallel

ISA-type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. It is possible to use the

parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs, as detailed in the sections that

follow. All interrupt signaling is provided through the seven multifunction terminals, MFUNC0−MFUNC6.

3.7.1

PC Card Functional and Card Status Change Interrupts

PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are

indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by

16-bit I/O PC Cards and by CardBus PC Cards.

Card status change (CSC)-type interrupts are defined as events at the PC Card interface that are detected by the

PCI1520 and may warrant notification of host card and socket services software for service. CSC events include both

card insertion and removal from PC Card sockets, as well as transitions of certain PC Card signals.

Table 3−9 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and

functional interrupt sources are dependent on the type of card inserted in the PC Card socket. The three types of cards

that can be inserted into any PC Card socket are:

•

16-bit memory card

•

16-bit I/O card

•

CardBus cards

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