Silan

Semiconductors

SC84510

HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD

Rev: 1.0

2000.12.31

7

(C) PS/2 mouse Data Transmission:

(a) SC84510 generates the clocking signal when sending data to and receiving data from the system.

(b) The system requests SC84510 receive system data output by forcing the DATA line to an inactive level and

allowing CLKlinetogotoanactivelevel.

(c) Data transmission frame:

Bit

Function

1

Start bit (always 0)

2~9

Data bits (D0~D7)

10

Parity bit (odd parity)

11

Stop bit (always 1)

(d) Data Output (data from SC84510 to system):

If CLK is low (inhibit status), data is no transmission.

If CLK is high and DATA is low (request-to-send), data is updated. Data is received from the system and

no transmission are started by SC84510 until CLK and DATA both high. If CLK and DATA are both high, the

transmission is ready. DATA is valid prior to the falling edge of CLK and beyond the rising edge of CLK.

During transmission, SC84510 check for line contention by checking for an inactive level on CLK at intervals

not to exceed 100

µ sec. Contention occurs when the system lowers CLK to inhibit SC84510 output after

SC84510 has started a transmission. If this occurs before the rising edge of the tenth clock, SC84510 internal

store its data in its buffer and returns DATA and CLK to an active level. If the contention does not occur by the

tenth clock, the transmission is complete.

Following a transmission, the system inhibits SC84510 by holding CLK low until it can service the input or

until the system receives a request to send a response from SC84510.

(e) Data Input (from system to SC84510):

System first check if SC84510 is transmitting data. If SC84510 is transmitting, the system can override

the output forcing CLK to an inactive level prior to the tenth clock. If SC84510 transmission is beyond the

tenth clock, the system receives the data. If SC84510 is not transmitting or if the system choose to override

the output, the system force CLK to an inactive level for a period of not less than 100

µ sec while preparing for

output. When the system is ready to output start bit (0), it allows CLK go to active level. If request-to-send is

detected, SC84510 clocks 11 bits. Following the tenth clock SC84510 checks for an active level on the DATA

line, and if found, force DATA low, and clock once more. If occurs framing error, SC84510 continue to clock

until DATA is high, then clocks the line control bit and request a Resend. When the system sends out a

command or data transmission that requires a response, the system waits for SC84510 to response before

sending its next output.