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ST72561 Datasheet(PDF) 185 Page - STMicroelectronics |
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ST72561 Datasheet(HTML) 185 Page - STMicroelectronics |
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185 / 262 page ![]() ST72561 185/262 beCAN CONTROLLER (Cont’d) 10.9.4.6 Bit Timing The bit timing logic monitors the serial bus-line and performs sampling and adjustment of the sample point by synchronizing on the start-bit edge and re- synchronizing on the following edges. Its operation may be explained simply by splitting nominal bit time into three segments as follows: – Synchronization segment (SYNC_SEG): a bit change is expected to occur within this time seg- ment. It has a fixed length of one time quantum (1 x tCAN). – Bit segment 1 (BS1): defines the location of the sample point. It includes the PROP_SEG and PHASE_SEG1 of the CAN standard. Its duration is programmable between 1 and 16 time quanta but may be automatically lengthened to compen- sate for positive phase drifts due to differences in the frequency of the various nodes of the net- work. – Bit segment 2 (BS2): defines the location of the transmit point. It represents the PHASE_SEG2 of the CAN standard. Its duration is programma- ble between 1 and 8 time quanta but may also be automatically shortened to compensate for neg- ative phase drifts. – Resynchronization Jump Width (RJW): de- fines an upper bound to the amount of lengthen- ing or shortening of the bit segments. It is programmable between 1 and 4 time quanta. To guarantee the correct behaviour of the CAN controller, SYNC_SEG + BS1 + BS2 must be greater than or equal to 5 time quanta. For a detailed description of the CAN resynchroni- zation mechanism and other bit timing configura- tion constraints, please refer to the Bosch CAN standard 2.0. As a safeguard against programming errors, the configuration of the Bit Timing Registers CBTR1 and CBTR0 is only possible while the device is in Initialization mode. Figure 105. Bit Timing Figure 106. CAN Frames (Part 1of 2) SYNC_SEG BIT SEGMENT 1 (BS1) BIT SEGMENT 2 (BS2) NOMINAL BIT TIME 1 x tCAN tBS1 tBS2 SAMPLE POINT TRANSMIT POINT Data Field 8 * N Control Field 6 Arbitration Field 12 CRC Field 16 Ack Field 7 ID DLC CRC Data Frame (Standard identifier) 44 + 8 * N 2 Inter-Frame Space or Overload Frame Inter-Frame Space EOF |
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