CY28343
Document #: 38-07369 Rev. *A
Page 6 of 10
Maximum Ratings[5]
Maximum Input Voltage Relative to VSS: ............. VSS – 0.5V
Maximum Input Voltage Relative to VSS: ............ VSS + 0.7V
Storage Temperature: ................................ –65°C to + 150°C
Operating Temperature: .................................... 0°C to +70°C
Maximum ESD Protection:...........................................2000V
Maximum Power Supply: ................................................5.5V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any volt-
age higher than the maximum rated voltages to this circuit. For
proper operation, Vin and Vout should be constrained to the
range:
VSS < (Vin or Vout) < VDD
Unused inputs must always be tied to an appropriate logic volt-
age level (either VSS or VDD).
Notes:
5.
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
6.
Unused inputs must be held high or low to prevent them from floating.
7.
All differential output terminals are terminated with 120
Ω/16 pF as shown in Figure 4.
8.
Refers to the transition of non-inverting output.
9.
Time required for the integrated PL circuit to obtain phase lock of its feed back signal to its reference signal. For Phase lock specifications for propagation delay,
skew and jitter parameters given in the switching characteristics table are not applicable.
DC Parameters[6]: TA = 0°C to +70°C
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage
SDATA, SCLK
1.0
V
VIH
Input High Voltage
2.2
V
VIL
CLKIN Input Low Voltage
(SDR Mode, VDD_3.3V = 3.3V)
CLKIN, FBIN_SDR
–0.3
0.8
V
VIL
CLKIN Input Low Voltage
(DDR Mode, VDD_2.5V = 2.5V)
CLKIN, FBIN_DDR
–0.3
0.7
V
VIH
CLKIN Input High Voltage
(SDR Mode, VDD_3.3V = 3.3V)
CLKIN, FBIN_SDR
2.0
VDD + 0.3
V
VIH
CLKIN Input High Voltage
(DDR Mode, VDD_2.5V = 2.5V)
CLKIN, FBIN_DDR
1.7
VDD + 0.3
V
IOZ
High-Impedance Output Current
VO = GND or
VO = VDD
–10
10
mA
IDDQ
Dynamic Supply Current[7]
FO = 133 MHz
235
300
ma
Cin
Input Pin Capacitance
4pF
Table 5. AC Parameters for DDRT/C (0:5): VDD_2.5V = 2.5V ±5%, AVDD_3.3V = 3.3V ±5%, TA = 0°C to +70°C
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
fCLK
Operating Clock Frequency
VDD_2.5V = 2.5V ±5%
99
170
MHz
tDCI
Input Clock Duty Cycle
45
55
%
tDCO
Output Clock Duty Cycle
47
50
53
%
tLOCK[9]
Maximum PLL Lock Time
1.5
ms
Tr/Tf
Output Clocks Slew Rate
20% to 80% of VDD_2.5V
1.0
2.3
V/ns
tpZL, tpZH
Output Enable Time[8](all outputs)
3
5
ns
tpLZ, tpHZ
Output Disable Time[8](all outputs)
3
5
ns
tHPJ
Half-Period Jitter
@100 MHz and 133 MHz
90
125
ps
tPHASE
Phase Error
@133 MHz
200
ps
tSKEW
Any Output to Any Output Skew[7]
150
ps
VOUT
Output Voltage Swing[7]
1.1
VDD – 0.4
V
Vx
Output Crossing Voltage[7]
(VDD/2) – 0.2
VDD/2
(VDD/2) + 0.2
V
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