LM1205 datasheet(13/24 Pages) NSC

13 / 24 page

Circuit Description (Continued)

CONTRAST CONTROL

Figure 9 is a simplified schematic of the Contrast Control

circuit The output of this circuit is common to all three chan-

nels A reference voltage is generated by Z2 Q34 Q35

R30 and R31 Q36 Q39 and Q41 are all current sources

that are controlled by the reference voltage The contrast

signal has a 0V to 4V range with its input at pin 12 R32 is

used for current limiting any voltage surge that may occur at

pin 12 Note that the input stage (Q37 Q38 and Q42) are

all PNP transistors This configuration is necessary for oper-

ation down to near ground At Q44 the input voltage is con-

verted to a current by R33 The input stage will apply the

same voltage across R33 as is applied at the input and with

no temperature variations from the transistors Q37 is con-

nected to a current source (Q36) to keep a constant current

flow through Q37 and a predictable diode voltage for the

base-emitter of Q37 Q40 is connected as a diode and is

biased by the current source Q39 The current through Q40

is mirrored into Q43 giving a current bias for Q42 Again this

is done to give a predictable diode voltage for Q42 Q41 is a

current source for both Q38 and Q42 With the current

through Q42 already established the rest of the current

from Q41 flows through Q38 As one can see the input volt-

age is accurately reflected across R33 with no temperature

coefficients from the input stage of the contrast control cir-

cuit

Pin 1 of the contrast control output is held at a constant

voltage two diode drops below

VCC To generate this ref-

erence the base of Q51 is held at exactly

VCC R44 and

R45 form a voltage divider With both Q53 and Q54 con-

nected as diodes the voltage at the junction of R44 and R45

VCC plus one diode drop Q52 is a buffer to this refer-

ence voltage generating exactly

VCC at its emitter Q51 is

used to drive the bases of Q49 and Q50 to one diode drop

below the reference voltage Q50 is used to further buffer

the reference voltage to the base of Q9 (see

Figure 8 ) and

the corresponding transistors in the other channels Q48 is

used to bias the collector of Q49 to

VCC the same volt-

age as the collector of Q47 when the differential pair is bal-

anced This keeps the characteristics of Q47 and Q49 well

matched Going back to Q44 and R33 these parts set up a

current source that varies the current through R36 With a

2V contrast voltage the differential pair is balanced mean-

ing that the voltage drop across R36 is

VCC Q45 buffers

the voltage at R36 driving the bases of Q46 and Q47 Q46

further buffers the voltage driving the base of Q8 (see

Fig-

ure 8 ) and the corresponding transistors in the other two

channels In the balanced condition the voltage at pin 2 will

also be two diode drops below

VCC giving a well bal-

anced drive to the differential pair consisting of Q8 and Q9

in the video amplifier input stage With the contrast voltage

set to 0V the voltage at pin 2 will increase by about 400 mV

to 500 mV A 4V contrast voltage decreases the voltage at

pin 2 by about 400 mV to 500 mV from the balanced condi-

tion Reviewing

Figure 8 note that decreasing the voltage at

pin 2 will decrease the current flow through Q8 Thus the

current flow through Q9 increases increasing the gain of

the LM1205LM1207 So increasing the contrast control

voltage at pin 12 increases the gain of the LM1205

LM1207 The contrast control voltage from Q46 and Q50 is

common to all three channels To minimize crosstalk it is

necessary to add a decoupling capacitor of 01 mF across

R37 and R40 Since this can only be done externally these

two nodes are brought out to pins 1 and 2 The 30X resistor

is added in series with the capacitor for improving stability

To prevent a destructive current surge due to shorting either

pins 1 or 2 to ground R38 was added for current limiting

DRIVE CONTROL

Figure 10 is a simplified schematic of the Drive Control cir-

cuit Each channel has its own drive control circuit This

circuit is almost identical to

Figure 9 the contrast control

circuit It will be easier to cover the differences between the

two circuits instead of going through virtually the same cir-

cuit description Note that the input stage is exactly the

same The generation of the reference voltage at the right

hand side of

Figure 10 is slightly different than the circuit in

Figure 9 ln the drive control circuit the reference voltage at

the base of Q72 is to be

VCC In the contrast control

circuit the reference voltage at the base of Q51 was to be

VCC To generate the

VCC R57 and R58 forma2to1

voltage divider With the two to one ratio it is now necessary

to have three transistors connected as diodes which are

Q74 Q75 and Q76 Q73 is the buffer for this voltage divider

and its emitter is exactly

VCC with temperature compen-

sation R52 and R53 also differ from their corresponding

resistors in

Figure 9 R36 and R39 The value difference is

so the base of Q66 is also at

VCC when the input drive

voltage is at 2V R38 in

Figure 9 was needed for current

limiting at the output pins Since each channel has its own

drive control circuit no filtering is required eliminating the

need for external pins With no external pins no current limit-

ing is necessary thus the 1k resistor is not used in the drive

control circuit

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