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DP7419 Datasheet(PDF) 1 Page - Copal Electronics |
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DP7419 Datasheet(HTML) 1 Page - Copal Electronics |
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1 / 16 page  DP7419 © NIDEC COPAL ELECTRONICS CORP. 1 Doc. No. MD-2115 Rev. H Characteristics subject to change without notice Dual Digital Potentiometers (DP) with 64 Taps and 2-wire Interface FEATURES Two linear-taper digital potentiometers 64 resistor taps per potentiometer End to end resistance 2.5k , 10k , 50k or 100k Potentiometer control and memory access via 2-wire Interface (I 2C like) Low wiper resistance, typically 80 Four non-volatile wiper settings for each potentiometer Recall of wiper settings at power up 2.5 to 6.0 volt operation Standby current less than 1µA 1,000,000 nonvolatile WRITE cycles 100 year nonvolatile memory data retention 24-lead SOIC and 24-lead TSSOP Write protection for data register PIN CONFIGURATION SOIC (W) (top view) VCC 124 NC RL0 223 NC RH0 322 NC RW0 421 NC A2 520 A0 WP ¯¯¯ 619 NC SDA 718 A3 A1 817 SCL RL1 916 NC RH1 10 15 NC RW1 11 14 NC GND 12 13 NC CAT 5419 TSSOP (Y) (top view) SDA 124 WP ¯¯¯ A1 223 A2 RL1 322 RW0 RH1 421 RH0 RW1 520 RL0 GND 619 VCC NC 718 NC NC 817 NC NC 916 NC NC 10 15 NC SCL 11 14 A0 A3 12 13 NC CAT 5419 DESCRIPTION The DP7419 is two Digital Potentiometers (DPs) integrated with control logic and 16 bytes of NVRAM memory. A separate 6-bit control register (WCR) independently controls the wiper tap position for each DP. Associated with each wiper control register are four 6- bit non-volatile memory data registers (DR) used for storing up to four wiper settings. Writing to the wiper control register or any of the non-volatile data regis- ters is via a 2-wire serial bus (I 2C-like). On power-up, the contents of the first data register (DR0) for each of the two potentiometers is automatically loaded into its respective wiper control registers (WCR). The Write Protection (WP ¯¯¯) pin protects against inadvertent programming of the data register. The DP7419 can be used as a potentiometer or as a two terminal, variable resistor. It is intended for circuit level or system level adjustments in a wide variety of applications. FUNCTIONAL DIAGRAM For Ordering Information details, see page 15. RW0 RW1 RH0 SDA SCL A0 A1 A2 A3 RH1 RL0 RL1 NONVOLATILE DATA REGISTERS WIPER CONTROL REGISTERS CONTROL LOGIC 2-WIRE BUS INTERFACE WP |
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