EMC1182 datasheet(32/48 Pages) MICROCHIP

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Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Datasheet

Revision 1.0 (07-11-13)

SMSC EMC1182

DATASHEET

6.9

Therm Limit Registers

The Therm Limit Registers are used to determine whether a critical thermal event has occurred. If the

measured temperature exceeds the Therm Limit, the THERM pin is asserted. The limit setting must

match the chosen data format of the temperature reading registers.

Unlike the ALERT / THERM2 pin, the THERM pin cannot be masked. Additionally, the THERM pin will

be released once the temperature drops below the corresponding threshold minus the Therm

Hysteresis.

6.10

Channel Mask Register 1Fh

The Channel Mask Register controls individual channel masking. When a channel is masked, the

ALERT / THERM2 pin will not be asserted when the masked channel reads a diode fault or out of limit

error. The channel mask does not mask the THERM pin.

Bit 1 - EXTMASK - Masks the ALERT / THERM2 pin from asserting when the External Diode channel

is out of limit or reports a diode fault.



‘0’ (default) - The External Diode channel will cause the ALERT / THERM2 pin to be asserted if it

is out of limit or reports a diode fault.



‘1’ - The External Diode channel will not cause the ALERT / THERM2 pin to be asserted if it is out

of limit or reports a diode fault.

Bit 0 - INTMASK - Masks the ALERT / THERM2 pin from asserting when the Internal Diode

temperature is out of limit.



‘0’ (default) - The Internal Diode channel will cause the ALERT / THERM2 pin to be asserted if it

is out of limit.



‘1’ - The Internal Diode channel will not cause the ALERT / THERM2 pin to be asserted if it is out

of limit.

Table 6.9 Therm Limit Registers

ADDR.

R/W

DEFAULT

19h

R/W

External

Diode Therm

Limit

128

55h

(85°C)

20h

R/W

Internal Diode

Therm Limit

128

55h

(85°C)

21h

R/W

Therm

Hysteresis

128

0Ah

(10°C)

Table 6.10 Channel Mask Register

ADDR.

R/W

DEFAULT

1Fh

R/W

Channel

Mask

---

EXT

MASK

INT

MASK

00h

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