HOST_TXP

HOST_TXN

HOST_RXP

HOST_RXN

CH2_EQ1

CFG2

CH2_EQ2

HOST_DM

HOST_DP

R2

DNI

C10

100nF

C11

100nF

VCC_3P3V

C9

10uF

TUSB1002

24-PIN RGE

U1

1

MODE

7

RX1N

8

RX1P

9

GND

10

TX2N

11

TX2P

12

RX2P

RX2N

GND

TX1P

TX1N

RSVD1

GND

C2

100nF

C1

100nF

C3

100nF

C5

100nF

C6

100nF

C4

100nF

J1

USB3_TYPEA_CONNECTER

VBUS 1

DM 2

DP 3

GND 4

SSRXN 5

SSRXP 6

GND 7

SSTXN 8

SSTXP 9

SHIELD0 10

SHIELD1 11

R1

1M

C7

100nF

C8

0.001uF

USB_VBUS

VCC_3P3V

CONNECT TO

USB3.1 HOST

VCC_3P3V

CFG1

CH1_EQ2

CH1_EQ1

19

20

21

22

23

24

25

VCC_3P3V

2

3

4

5

6

Copyright © 2016, Texas Instruments Incorporated

19

TUSB1002

www.ti.com

SLLSEU4A – MAY 2016 – REVISED MAY 2016

Product Folder Links: TUSB1002

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Copyright © 2016, Texas Instruments Incorporated

8.2.2 Detailed Design Procedure

The TUSB1002 differential receivers and transmitters have internal BIAS and termination. For this reason, the

TUSB1002 must be connected to the USB3.1 host and receptacle through external A/C coupling capacitors. In

this example as depicted in Table 4, 100 nF capacitors are placed on TX2P/N, RX1P/N, and TX1P/N. No A/C

coupling capacitors are placed on the RX2P/N because it is assumed the device downstream of the TUSB1002

will have A/C coupling capacitor on its transmitter as defined by the USB 3.1 specification.

Figure 18. Host Implementation Schematic

The USB3.1 Dual channel operation is used in this example. Mode pin should be left floating (unconnected)

when using this mode.

In this example, the USB3.1 Host does not support a GPIO for indicating system Sx state or low power states

and therefore the SLP_S0# pin can be left floating.

The TUSB1002 compensates for channel loss in both the upstream (D to C) and downstream direction (A to B).

This is done by configuring the CH1_EQ[2:1] and CH2_EQ[2:1] pins to the equalization setting that matches as

close possible to the channel insertion loss. In this particular example, CH1_EQ[2:1] is for path A to B which is

the channel between USB3.1 host and the TUSB1002, and CH2_EQ[2:1] is for path C to D which is the channel

between TUSB1002 and the USB3.1 receptacle.

The TUSB1002 supports 5 levels of DC gain that are selected by the CFG[2:1] pins. Typically, the DC gain

should be set to 0 dB but may need to be adjusted to correct any one of the following conditions:

gain should be used.

should be used.

3. Low frequency discontinuities in the channel resulting in DC component of the signal clipping the vertical eye

mask. For this case, a positive DC gain should be used.

across frequency. The CFG1 and CFG2 pins can both be left floating if these assumptions are true.