ST7MC1 datasheet(237/308 Pages) STMICROELECTRONICS

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ST7MC1/ST7MC2

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10-BIT A/D CONVERTER (ADC) (Cont’d)

When a conversion is complete:

– The EOC bit is set by hardware

– An interrupt request is generated if the ADCIE

bit in the MCCBCR register is set (see section

6.4.7 on page 37).

– The result is in the ADCDR registers and re-

mains valid until the next conversion has end-

ed.

To read the 10 bits, perform the following steps:

1. Poll the EOC bit or wait for EOC interrupt

2. Read ADCDRLSB

3. Read ADCDRMSB

The EOC bit is reset by hardware once the AD-

CDRMSB is read.

To read only 8 bits, perform the following steps:

1. Poll the EOC bit or wait for EOC interrupt

2. Read ADCDRMSB

The EOC bit is reset by hardware once the AD-

CDRMSB is read.

Changing the conversion channel

The application can change channels during con-

version. In this case the current conversion is

stopped and the A/D converter starts converting

the newly selected channel.

ADCCR consistency

If an End Of Conversion event occurs after soft-

ware has read the ADCDRLSB but before it has

read the ADCDRMSB, there would be a risk that

the two values read would belong to different sam-

ples.

To guarantee consistency:

– The ADCDRMSB and the ADCDRLSB are

locked when the ADCCRLSB is read

– The ADCDRMSB and the ADCDRLSB are un-

locked when the MSB is read or when ADON

is reset.

Thus, it is mandatory to read the ADCDRMSB just

after reading the ADCDRLSB. Otherwise the AD-

CDR register will not be updated until the AD-

CDRMSB is read.

10.8.4 Low Power Modes

Note: The A/D converter may be disabled by re-

setting the ADON bit. This feature allows reduced

power consumption when no conversion is need-

ed.

10.8.5 Interrupts

1)The ADCIE bit is in the MCCBCR register (see

section 6.4.7 on page 37)

Mode

Description

WAIT

No effect on A/D Converter

HALT

A/D Converter disabled.

After wake up from Halt mode, the A/D

Converter requires a stabilization time

tSTAB (see Electrical Characteristics)

before accurate conversions can be

performed.

Interrupt

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

End of Conver-

sion

EOC

ADCIE1)

Yes

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