LTC4355 datasheet(13/20 Pages) LINEAR

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LTC4419

4419f

For more information www.linear.com/LTC4419

applicaTions inForMaTion

switch-over threshold. When V1 recovers, it needs to be

qualified for 64ms before it is reconnected to OUT. OUT

gets discharged by ROUT and is connected to V2 once its

voltage is 50mV less than V2.

Reverse Voltage Blocking

The LTC4419 blocks reverse voltages on supply pins V1

and V2 up to –15V relative to GND and up to –39V relative

to OUT. Transient voltage suppressors (TVS) connected to

V1 and V2 must be bidirectional and capacitors connected

to these pins must be rated to handle reverse voltages. A

reverse voltage on V2 does not disrupt V1 operation and

vice versa.

Freshness Seal

Freshness seal mode prevents V2 battery discharge by

keeping V2 disconnected from OUT even if V1 is absent

or invalid. Very little current is drawn from V2—typically

just 120nA. The following sequence (refer to Figure 8)

puts the LTC4419 in freshness seal mode:

1. Power up V2 while holding V1 low and wait for at least

10ms.

2. Drive V2ON below 50mV.

3. Power up V1 and ADJ for at least 94ms. Freshness seal

is enabled.

Engage this mode if V2 is a backup battery either during

storage or during shipment. Once freshness seal has been

engaged, if V1 is disconnected, V2 stays disconnected

from OUT. Freshness seal is automatically disabled the

next time V1 is revalidated. Limit V2ON pin capacitance

to less than 10nF in order to prevent freshness seal mode

from accidentally being engaged.

Design Example

In Figure 9, the LTC4419 prioritizes between a 5V supply

connected to V1 and a 7.4V 2-cell Li-Ion battery connected

to V2. The system is designed to switch OUT to V2 when

V1 drops below 4V, provide early power failure warning

when V1 drops below 4.5V and low battery warning when

the backup battery voltage drops below 6V. Maximum

anticipated load current is 100mA and maximum allowed

output droop is 100mV. Output rising slew rate is limited

to <0.1V/µs and V1 and V2 input capacitors are limited to

10µF to avoid large inrush current. 1% tolerance resistors

are used. ADJ and CMP pin leakages are ignored as their

design impact is small.

First choose total resistive divider current to be ~10µA

for V1 and ~5µA for V2. For the 5V supply, this results in:

+R2+R3=

10µA

=500kΩ

(14)

Since desired switchover threshold, VSW1, and the total

divider impedance are known, use equation 1 to first

calculate R3. Using R3 and equation 2, calculate R1 and

R2. Rewriting equation 1 results in:

+R2

(

)= VTHA • R1+R2+R3

(

)

VSW1

(15)

FSEAL

ENABLED

DRIVEN LOW

EXTERNALLY

94ms

1.116V

4419 F08

1.8V

10ms

1.8V

V2ON

ADJ

Figure 8. Freshness Seal Engage Procedure

365k

88.7k

2.2µF

44.2k

INPUT

2-CELL

Li-Ion

7.4V

1.37M

RSN1

0.5

95.3k

OUT

PFV1

V2UV

CMPOUT1

CMPOUT2

ADJ

CMP1

CMP2 GND

4419 F09

LTC4419

2.2µF

COUT

15µF

Figure 9. Design Example

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