®

AS7C1025

AS7C31025

3/23/01; v.1.0

Alliance Semiconductor

P. 6 of 9

Data retention waveform

AC test conditions

Notes

2

This parameter is sampled, but not 100% tested.

3

For test conditions, see AC Test Conditions, Figures A, B, and C.

5

This parameter is guaranteed, but not 100% tested.

6WE is High for read cycle.

7CE and OE are Low for read cycle.

8

Address valid prior to or coincident with CE transition Low.

9

All read cycle timings are referenced from the last valid address to the first transitioning address.

10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.

11 All write cycle timings are referenced from the last valid address to the first transitioning address.

12 NA.

13 2V data retention applies to commercial temperature operating range only.

14 C=30pF, except all high Z and low Z parameters, where C=5pF.

Parameter

Symbol

Test conditions

Min

Max

Unit

CE

≥ V

2.0

–

V

Data retention current

–500

µA

Chip enable to data retention time

0–

ns

Operation recovery time

–ns

Input leakage current

| I

–1

µA

CE

Data retention mode

255W

– 5V output load: see Figure B or Figure C.

– Input pulse level: GND to 3.0V. See Figure A.

– Input rise and fall times: 2 ns. See Figure A.

– Input and output timing reference levels: 1.5V.

C(14)

320W

GND

+3.3V

168W

Thevenin equivalent:

+1.728V (5V and 3.3V)

Figure C: 3.3V Output load

255W

C(14)

480W

GND

+5V

Figure B: 5V Output load

10%

90%

10%

90%

GND

+3.0V

Figure A: Input pulse

2 ns