CS8405A

DS469PP4

23

8.13

User Data Buffer Control (13h)

UD - User bit data pin (U) direction specifier

Default = ‘0’

0 - The U pin is an input. The User bit data is latched in on both rising and falling edges of

OLRCK. This setting also chooses the U pin as the source for transmitted U data.

1 - The U pin is an output. The received U data is clocked out on both rising and falling edges

of ILRCK. This setting also chooses the U data buffer as the source of transmitted U data.

UBM1:0 - Sets the operating mode of the AES3 User bit manager

Default = ‘00’

00 - Transmit all zeros mode

01 - Block mode

10 - Reserved

11 - Reserved

EFTUI - E to F U-data buffer transfer inhibit bit (valid in block mode only).

Default = ‘0’

0 - Allow U-data E to F buffer transfers

1 - Inhibit U-data E to F buffer transfer

8.14

Channel Status bit or User bit Data Buffer (20h - 37h)

Either the channel status data buffer E or the separate user bit data buffer E (provided UBM bits are set to block

mode) is accessible through these register addresses.

8.15

CS8405A I.D. and Version Register (7Fh) (Read Only)

ID3:0 - ID code for the CS8405A. Permanently set to 0110

VER3:0 - CS8405A revision level. Revision A is coded as 0001

7

6

5

43210

0

0

0

UD

UBM1

UBM0

0

EFTUI

7

6

5

43210

ID3

ID2

ID1

ID0

VER3

VER2

VER1

VER0