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P89LPC930FDH Datasheet(PDF) 50 Page - NXP Semiconductors |
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P89LPC930FDH Datasheet(HTML) 50 Page - NXP Semiconductors |
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50 / 55 page ![]() Philips Semiconductors P89LPC930/931 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 05 — 15 December 2004 50 of 55 9397 750 14472 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Fig 18. SPI slave timing (CPHA = 1). tCLCL tSPICLKH tSPICLKL tSPILEAD tSPICLKH tSPICLKL tSPILAG tSPIDSU tSPIDH tSPIDH tSPIDSU tSPIR tSPIA tSPIOH tSPIDIS tSPIR Slave MSB/LSB out Not defined MSB/LSB in LSB/MSB in Slave LSB/MSB out tSPIDV tSPIOH tSPIDV tSPIOH tSPIDV tSPIR tSPIF tSPIR tSPIF SS SPICLK (CPOL = 0) (input) 002aaa159 SPICLK (CPOL = 1) (input) MISO (output) MOSI (input) tSPIDSU Fig 19. Shift register mode timing. 0 1 23 45 6 7 Valid Valid Valid Valid Valid Valid Valid Valid tXLXL 002aaa425 Set TI Set RI tXHQX tQVXH tXHDV tXHDX Clock Output Data Write to SBUF Input Data Clear RI Fig 20. External clock timing. tCHCL tCLCX tCHCX tC tCLCH 002aaa416 0.2 VDD + 0.9 0.2 VDD - 0.1 V VDD - 0.5 V 0.45 V |
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