CLC1001 datasheet(15/17 Pages) EXAR

15 / 17 page

Data Sheet

15/17

Rev 1G

Driving Capacitive Loads

Increased phase delay at the output due to capacitive

loading can cause ringing, peaking in the frequency

response, and possible unstable behavior. Use a series

resistance, RS, between the amplifier and the load to help

improve stability and settling performance. Refer to Figure

Input

Output

Figure 5. Addition of RS for Driving Capacitive Loads

Table 1 provides the recommended RS for various

capacitive loads. The recommended RS values result in

<=1dB peaking in the frequency response. The Frequency

Response vs. CL plots, on page 7, illustrates the response

of the CLC1001.

CL (pF)

RS (Ω)

-3dB BW (MHz)

266

228

192

100

155

470

4.3

Table 1: Recommended RS vs. CL

For a given load capacitance, adjust RS to optimize the

tradeoff between settling time and bandwidth. In general,

reducing RS will increase bandwidth at the expense of

additional overshoot and ringing.

Overdrive Recovery

An overdrive condition is defined as the point when either

one of the inputs or the output exceed their specified

voltage range. Overdrive recovery is the time needed for

the amplifier to return to its normal or linear operating

point. The recovery time varies, based on whether the

input or output is overdriven and by how much the range

is exceeded. The CLC1001 will typically recover in less

than 25ns from an overdrive condition. Figure 6 shows the

CLC1001 in an overdriven condition.

-6

-4

-2

-3

-2

-1

100

150

200

250

300

350

400

450

Time (us)

Output

Input

G = 10

Figure 6. Overdrive Recovery

Layout Considerations

General layout and supply bypassing play major roles in

high frequency performance. has evaluation boards to

use as a guide for high frequency layout and as an aid in

device testing and characterization. Follow the steps below

as a basis for high frequency layout:

▪ Include 6.8µF and 0.1µF ceramic capacitors for power

supply decoupling

▪ Placethe6.8µFcapacitorwithin0.75inchesofthepowerpin

▪ Placethe0.1µFcapacitorwithin0.1inchesofthepowerpin

▪ Remove the ground plane under and around the part,

especially near the input and output pins to reduce

parasitic capacitance

▪ Minimize all trace lengths to reduce series inductances

Refer to the evaluation board layouts below for more

information.

Evaluation Board Information

The following evaluation boards are available to aid in the

testing and layout of these devices:

Evaluation Board #

Products

CEB002

CLC1001 in SOT23-5

CEB003

CLC1001 in SOIC-8

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