Rev 1.1

vicorpower.com

Page 13 of 17

05/2016

800 927.9474

PI3302-03

Layout Guidelines

To optimize maximum efficiency and low noise performance

from a PI3302-03 design, layout considerations are necessary.

Reducing trace resistance and minimizing high current loop

returns along with proper component placement will contribute

to optimized performance.

A typical buck converter circuit is shown in Figure 16. The

potential areas of high parasitic inductance and resistance are

the circuit return paths, shown as LR below.

importance since the AC currents are flowing through both of

them when Q1 is turned on. Figure 17, schematically, shows the

reduced trace length between input and output capacitors. The

shorter path lessens the effects that copper trace parasitics can

have on the PI3302-03 performance.

When Q1 is off and Q2 is on, the load current is supplied by the

loop inductance is important to reduce peak voltage excursions

The recommended component placement, shown in Figure 19,

used on the PI3302-03 evaluation board.

C

OUT

C

IN

V

IN

Figure 16 — Typical Buck Converter

C

OUT

V

IN

C

IN

Figure 17 — Current flow: Q1 closed

C

OUT

V

IN

C

IN

Figure 18 — Current flow: Q2 closed

C

OUT

C

IN

V

IN

V

OUT

GND

GND

VSW

Figure 19 — Recommended component placement and

metal routing