MTD6508

DS20005359A-page 2

 2015 Microchip Technology Inc.

Package Types

Functional Block Diagram

*Includes Exposed Thermal Pad (EP); see Table 3-1.

MTD6508

4x4 UQFN-16*

MTD6508

3x3 UDFN-10*

Note: The DIR, SS and RT pins that are not available on UDFN-10 Package are internally pulled down. SR1 and

SR2 are connected by a fixed internal resistor (25 kΩ).

2

OUT2

FG

RT

PWM

FG3_SEL

EP

16

1

15 14 13

3

4

12

11

10

9

567

8

17

OUT1

FG3_SEL

1

2

3

4

10

9

8

7 OUT3

PWM

FG

EP

11

5

6

OUT2

GND

Thermal

Protection

OUT1

OUT2

CPU + Peripherals

PWM

FG

OUT3

Short-Circuit

Protection

Motor Phase

Detection Circuit

Overcurrent

Protection

GND

Nonvolatile

Memory

Slew Rate

Control

SR1

SR2

RT

SS

DIR

FG3_SEL