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MD2131 Datasheet(PDF) 3 Page - Supertex, Inc

Part # MD2131
Description  High Speed Ultrasound Beamforming Source Driver
PDF  8 Pages
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Manufacturer  SUTEX [Supertex, Inc]
Direct Link  http://www.supertex.com
Logo SUTEX - Supertex, Inc

MD2131 Datasheet(HTML) 3 Page - Supertex, Inc

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MD2131
Supertex inc.
www.supertex.com
Doc.# DSFP-MD2131
C102412
Aperture DAC Characteristics
(Over operating conditions unless otherwise specified, V
LL = +3.3V, VDD = +5V, RFB = 50kΩ, TA = 25°C)
Sym
Parameter
Min
Typ
Max
Units Conditions
Reso
Resolution
-
8
-
Bits
---
E
LINEAR
Linearity error
-
1.0
3.0
%
±% of FSR
E
DNL
Differential nonlinearity error
-
0.6
1.0
%
±% of FSR
MON
Monotonicity
-
8
-
Bits
---
V
REF
External reference voltage
1.25
-
2.5
V
---
Logic and Data Input Characteristics
(Over operating conditions unless otherwise specified, V
LL = +3.3V, VDD = +5V, RFB = 50kΩ, TA = 0 - 70°C)
Sym
Parameter
Min
Typ
Max
Units Conditions
V
IH
Input logic high voltage
0.8V
LL
-
V
LL
V
---
V
IL
Input logic low voltage
0
-
0.2V
LL
V
---
I
IH
Input logic high current
-
-
1.0
µA
---
I
IL
Input logic low current
-1.0
-
-
µA
---
AC Electrical Characteristics
(Over operating conditions unless otherwise specified, V
LL = +3.3V, VDD = +5V, RFB = 50kΩ, TA = 25°C)
Sym
Parameter
Min
Typ
Max
Units Conditions
t
ST
DAC to output setup time
-
-
10
µs
All caps 10nF, DAC = 0 to 255,
settle to 1LSB
t
r
Output current rise time
-
2.0
3.0
ns
1.0Ω resistor load to V
DD,
DAC = 85,
Angle = 45O,
V
REF = 2.5V
t
f
Output current fall time
-
2.0
3.0
t
dr
Input to output delay on rise
-
4.0
5.0
t
df
Input to output delay on fall
-
4.0
5.0
t
M
Delay time matching
-
±2.0
±3.0
ns
From PA to PB and device to device
t
J
Output jitter
-
50
-
ps
---
t
1
SDI valid to SCK setup time
0
2.0
-
ns
See serial interface timing diagram
t
2
SDI valid to SCK hold time
4.0
-
-
t
3
SCK high time (% of 1/f
SCK)
45
-
55
%
See serial interface timing diagram
t
4
SCK low time (% of 1/f
SCK)
45
-
55
t
5
CS pulse width
4.0
-
6.0
ns
See serial interface timing diagram
t
6
LSB SCK high to CS high
7.0
-
-
t
7
CS low to SCK high
7.0
-
-
t
8
SDO propagation delay from SCK
failing edge
-
-
10
t
9
CS high to SCK raising edge
7.0
-
-
t
10
CS high to LD raising edge
10
-
-
f
SCK
Serial clock maximum frequency
40
50
-
MHz ---
THD
Total harmonic distortion
-
-45
-40
dB
---
t
EN-OFF
EN fall to PA/PB turn OFF time
-
5.0
8.0
ns
50% to 90%
t
EN-ON
EN rise to PA/PB turn ON time
-
13.5
20.0
µs
50% to 10%



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