ESS Technology, Inc.

SAM0416-052201

3

ES3883 PRODUCT BRIEF

AUX14

39

I/O

Servo SCOR (S0S1), interrupt input, or general-purpose I/O.

AUX15

40

I/O

Interrupt input or general-purpose I/O.

DSC_D[7:0]

81,83,85,93,95,97,99,8

I/O

Data for programming to access internal registers.

DSC_S

10

I

Strobe for programming to access internal registers.

DCLK

12

O

Dual-purpose. DCLK is the MPEG decoder clock.

EXT_CLK

I

EXT_CLK is the external clock. EXT_CLK is an input during bypass PLL mode.

RESET_B

13

I

Video reset (active-low).

MUTE

15

O

Audio mute.

MCLK

17

I

Audio master clock.

TWS

19

I

Dual-purpose. TWS is the transmit audio frame sync.

SPLL_OUT

O

SPLL_OUT is the select PLL output.

TSD

21

I

Transmit audio data input.

TBCK

22

I

Transmit audio bit clock.

RWS

23

O

Dual-purpose. RWS is the receive audio frame sync.

SEL_PLL1

I

SEL_PLL[1:0] select the PLL clock frequency for the DCLK output.

RSTOUT_B

24

O

Reset output (active-low).

NC

2:4,27:30,76

No connect.

RSD

33

O

Dual-purpose. RSD is the receive audio data input.

SEL_PLL0

I

SEL_PLL0 and SEL_PLL1 select the PLL clock frequency for the DCLK output. Refer to the

table for pin 23.

RBCK

37

O

Dual-purpose. RBCK is the receive audio bit clock.

SER_IN

I

SER_IN is the serial input DSC mode:

0 = Parallel DSC mode.

1 = Serial DSC mode.

VSSAA

41,51

I

Audio analog ground.

VCM

42

I

ADC common mode reference (CMR) buffer output. CMR is approximately 2.25V. Bypass to

analog ground with 47-

µF electrolytic in parallel with 0.1 µF.

VREFP

43

I

DAC and ADC maximum reference. Bypass to video CMR (VCMR) with 10

µF in parallel with

0.1

µF.

VCCAA

44

I

Analog VCC, 5V.

AOR+, AOR-

45:46

O

Right channel output.

AOL-, AOL+

47:48

O

Left channel output.

MIC1

49

I

Microphone input 1.

MIC2

50

I

Microphone input 2.

VREF

52

I

Internal resistor divider generates CMR voltage. Bypass to analog ground with 0.1

µF.

VREFM

53

I

DAC and ADC minimum reference. Bypass to VCMR with 10

µF in parallel with 0.1 µF.

RSET

54

I

Full-scale DAC current adjustment.

COMP

55

I

Compensation pin.

VSSAV

56:57,62:63

I

Video analog ground

CDAC

58

O

Modulated chrominance output.

VCCAV

59,60

I

Video VCC, 5V

YDAC

61

O

Y luminance data bus for screen video port.

VDAC

64

O

Composite video output.

ACAP

65

I

Audio CAP

XOUT

71

O

Crystal output.

XIN

74

I

27-MHz crystal input.

PCLK

79

I/O

13.5-MHz pixel clock.

2XPCLK

80

I/O

27-MHz (2 times pixel clock).

HSYN_B

82

O

Horizontal sync (active-low).

VSYN_B

84

O

Vertical sync (active-low).

YUV[7:0]

86:89,92,94,96,98

I

YUV data bus for screen video port.

Table 1 Visba ES3883 Pin Description (Continued)

Name

Number

I/O

Definition

SEL_PLL1

SEL_PLL0

DCLK

0

0

Bypass PLL (input mode)

0

1

27 MHz (output mode)

1

0

32.4 MHz (output mode)

1

1

40.5 MHz (output mode)