ST26C32

2

Rev. 1.01

PIN CONFIGURATION

16 Lead PDIP (0.300”)

INPUT D

OUTPUT D+

OUTPUT D-

-ENABLE

OUTPUT C-

OUTPUT C+

INPUT C

INPUT A

OUTPUT A+

OUTPUT A-

ENABLE

OUTPUT B-

OUTPUT B+

INPUT B

GND

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

16 Lead SOIC (Jedec, 0.150”)

16

1

9

8

2

3

4

5

6

7

15

14

13

12

11

10

INPUT D

OUTPUT D+

OUTPUT D-

-ENABLE

OUTPUT C-

OUTPUT C+

INPUT C

INPUT A

OUTPUT A+

OUTPUT A-

ENABLE

OUTPUT B-

OUTPUT B+

INPUT B

GND

PIN DESCRIPTION

Pin #

Symbol

Type

Description

1

INPUT A-

I

Receiver A differential inverting input pin.

2

INPUT A+

I

Receiver A differential non-inverting input pin.

3

OUTPUT A

O

Receiver A output pin.

4

ENABLE

I

Gate control (active high). This pin is one of the two control pins which enables or disables all

four receivers.

5

OUTPUT B

O

Receiver B output pin.

6

INPUT B+

I

Receiver B differential non-inverting input pin.

7

INPUT B-

I

Receiver B differential inverting input pin.

8

GND

O

Signal and power ground.

9

INPUT C-

I

Receiver C differential inverting input pin.

10

INPUT C+

I

Receiver C differential non-inverting input pin.

11

OUTPUT C

O

Receiver C output pin.

12

-ENABLE

I

Gate control (active low). See ENABLE description

13

OUTPUT D

O

Receiver D output pin.

14

INPUT D+

I

Receiver D differential non-inverting input pin.

15

INPUT D-

I

Receiver D differential inverting input pin.

16

I

Power supply pin.