8-OUTPUT 3.3V PCIE CLOCK GENERATOR

4

OCTOBER 19, 2016

9FGL08 DATASHEET

Pin Descriptions, cont.

Test Loads

Alternate Terminations

The 9FGL family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with

IDT's "Universal" Low-Power HCSL Outputs” for details.

PIN #

PIN NAME

TYPE

DESCRIPTION

40

GND

GND

Ground pin.

41

DIF6

OUT

Differential true clock output

42

DIF6#

OUT

Differential Complementary clock output

43

vOE6#

IN

Active low input for enabling DIF pair 6. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

44

DIF7

OUT

Differential true clock output

45

DIF7#

OUT

Differential Complementary clock output

46

vOE7#

IN

Active low input for enabling DIF pair 7. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

47

VDDIO

PWR

Power supply for differential outputs

48

^CKPWRGD_PD#

IN

Input notifies device to sample latched inputs and start up on first high

assertion. Low enters Power Down Mode, subsequent high assertions exit

Power Down Mode. This pin has internal pull-up resistor.

49

EPAD

GND

Connect to Ground.

REF Output

33

REF Output Test Load

5pF

Zo = 50 ohms

Rs

Rs

Low-Power Differential Output Test Load

2pF

2pF

5 inches

Zo=100ohm

Note: The device can drive transmission line lengths greater

than those specified by the PCIe SIG

Terminations

Device

Zo (Ω)Rs (Ω)

9FGL0841

100

None needed

9FGL0851

100

7.5

9FGL08P1

100

Prog.

9FGL0841

85

N/A

9FGL0851

85

None needed

9FGL08P1

85

Prog.