MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order Number: MPC9350/D

Rev 3, 01/2002

1

Low Voltage PLL Clock Driver

The MPC9350 is a 2.5V and 3.3V compatible, PLL based clock

generator targeted for high performance clock distribution systems. With

output frequencies of up to 200 MHz and maximum output skews of 150

ps the MPC9350 is ideal for the most demanding clock tree designs. The

device offers 9 low skew clock outputs, each is configurable to support the

clocking needs of the various high-performance microprocessors

including the PowerQuicc II integrated communication microprocessor.

The extended temperature range of the MPC9350 supports

telecommunication and networking requirements. The devices employs a

fully differential PLL design to minimize cycle-to-cycle and long-term jitter.

Features

Functional Description

The MPC9350 generates high frequency clock signals and provides nine exact frequency-multiplied copies of the reference

clock signal. The internal PLL allows the MPC9350 to operate in frequency locked condition and to multiply the input reference

clock. The reference clock frequency and the divider in the internal feedback path determine the VCO frequency. Two selectable

PLL feedback frequency ratios are available on the MPC9350 to provide input frequency range flexibility. The FBSEL pin selects

between divide-by-16 or divide-by-32 of the VCO frequency for PLL feedback. This feedback divider must be selected to match

the VCO frequency range. With the available feedback output dividers the internal VCO of the MPC9350 is running at either 16x

or 32x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is either one half, one fourth or one

eighth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSELD

pins, respectively. The available output to input frequency ratios are 16:1, 8:1, 4:1 and 2:1. The REF_SEL pin selects the crystal

oscillator inputs or the LVCMOS compatible reference input (TCLK). TCLK also provides an external test clock in static test mode

when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode, the selected input reference clock is routed directly to

the output dividers without using the PLL. The test mode is intended for system diagnostics, test and debug purpose. This test

mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by deasserting

the OE pin (logic high state). In PLL mode, deasserting OE maintains PLL lock due to the internal feedback path. The MPC9350 is

fully 2.5V and 3.3V compatible and requires no external loop filter components. The on-chip crystal oscillator requires no external

components beyond a series resonant crystal. All inputs except the crystal oscillator interface accept LVCMOS signals while the

outputs provide LVCMOS compatible levels with the capability to drive terminated 50

W transmission lines. For series terminated

transmission lines, each of the MPC9350 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The

device is packaged in a 7x7 mm2 32-lead LQFP package.

FA SUFFIX

32 LEAD LQFP PACKAGE

CASE 873A

MPC9350

LOW VOLTAGE

3.3V AND 2.5V PLL

CLOCK GENERATOR

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com