PIC16C433 datasheet(39/126 Pages) MICROCHIP

39 / 126 page

 2002 Microchip Technology Inc.

Preliminary

DS41139B-page 37

PIC16C433

7.0

TIMER0 MODULE

The Timer0 module timer/counter has the following

features:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overflow from FFh to 00h

• Edge select for external clock

Figure 7-1 is a simplified block diagram of the Timer0

module.

Timer mode is selected by clearing bit T0CS

(OPTION<5>). In Timer mode, the Timer0 module will

increment every instruction cycle (without prescaler). If

the TMR0 register is written, the increment is inhibited

for the following two instruction cycles (Figure 7-2 and

Figure 7-3). The user can work around this by writing

an adjusted value to the TMR0 register.

Counter mode is selected by setting bit T0CS

(OPTION<5>). In Counter mode, Timer0 will increment

either on every rising or falling edge of pin RA4/T0CKI.

The incrementing edge is determined by the bit T0SE

(OPTION<4>). Clearing bit T0SE selects the rising

edge. Restrictions on the external clock input are dis-

cussed in detail in Section 7.2.

The prescaler is mutually exclusively shared between

the Timer0 module and the Watchdog Timer. The

prescaler assignment is controlled in software by con-

trol bit PSA (OPTION<3>). Clearing bit PSA will assign

the prescaler to the Timer0 module. The prescaler is

not readable or writable. When the prescaler is

assigned to the Timer0 module, pre-scale values of 1:2,

1:4, ..., 1:256 are selectable. Section 7.3 details the

operation of the prescaler.

7.1

Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-

ister overflows from FFh to 00h. This overflow sets bit

T0IF (INTCON<2>). The interrupt can be masked by

clearing bit T0IE (INTCON<5>). Bit T0IF must be

cleared in software by the Timer0 module Interrupt Ser-

vice Routine before re-enabling this interrupt. The

TMR0 interrupt cannot awaken the processor from

SLEEP, since the timer is shut-off during SLEEP. See

Figure 7-4 for Timer0 interrupt timing.

FIGURE 7-1:

TIMER0 BLOCK DIAGRAM

FIGURE 7-2:

TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

Note 1:

TOCS, TOSE, PSA, PS<2:0> (OPTION<5:0>).

The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram).

GP2/TOCKI/

TOSE

AN2/INT

TOCS

OSC/4

Programmable

Prescaler

Sync with

Internal

Clocks

TMR0

(2 T

CY delay)

Data Bus

PSA

PS<2:0>

Set Interrupt

Flag bit T0IF

on Overflow

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

TMR0

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

T0+1

T0+2

NT0

NT0+1

NT0+2

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0

executed

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0 + 2

Instruction

Executed

PIC16C433 Datasheet(PDF) 39 Page - Microchip Technology

PIC16C433 Datasheet(HTML) 39 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL