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STM32F745VG Datasheet(PDF) 157 Page - STMicroelectronics |
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STM32F745VG Datasheet(HTML) 157 Page - STMicroelectronics |
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157 / 227 page  DocID027590 Rev 4 157/227 STM32F745xx STM32F746xx Electrical characteristics 195 Figure 46. SPI timing diagram - slave mode and CPHA = 0 tsu(MI) Data input setup time Master mode 5.5 - - ns tsu(SI) Slave mode 4 - - th(MI) Data input hold time Master mode 4 - - th(SI) Slave mode 2 - - ta(SO) Data output access time Slave mode 7 - 21 tdis(SO) Data output disable time Slave mode 5 - 12 tv(SO) Data output valid time Slave mode 2.7≤VDD≤3.6V - 6.5 10 Slave mode 1.71≤VDD≤3.6V - 6.5 13 tv(MO) Master mode - 2 4 th(SO) Data output hold time Slave mode 1.71≤VDD≤3.6V 5.5 - - th(MO) Master mode 0 - - 1. Guaranteed by characterization results. 2. Excepting SPI1 with SCK IO pin mapped on PA5. In this configuration, Maximum achievable frequency is 40MHz. 3. Maximum Frequency of Slave Transmitter is determined by sum of Tv(SO) and Tsu(MI) intervals which has to fit into SCK level phase preceding the SCK sampling edge.This value can be achieved when it communicates with a Master having Tsu(MI)=0 while signal Duty(SCK)=50%. Table 76. SPI dynamic characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit |
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