STM32L071KB datasheet(102/136 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32L071xx

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DocID027101 Rev 3

SPI characteristics

Unless otherwise specified, the parameters given in the following tables are derived from

tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage

conditions summarized in Table 25.

Refer to Section 6.3.12: I/O current injection characteristics for more details on the

input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 72. SPI characteristics in voltage Range 1 (1)

1. Guaranteed by characterization results.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fSCK

1/tc(SCK)

SPI clock frequency

Master mode

MHz

Slave mode

receiver

Slave mode

Transmitter

1.71<VDD<3.6V

12(2)

2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI)

which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be

achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50%.

Slave mode

Transmitter

2.7<VDD<3.6V

16(2)

Duty(SCK)

Duty cycle of SPI clock

frequency

Slave mode

tsu(NSS)

NSS setup time

Slave mode, SPI

presc = 2

4*Tpclk

th(NSS)

NSS hold time

Slave mode, SPI

presc = 2

2*Tpclk

tw(SCKH)

tw(SCKL)

SCK high and low time

Master mode

Tpclk-2

Tpclk

Tpclk+

tsu(MI)

Data input setup time

Master mode

tsu(SI)

Slave mode

th(MI)

Data input hold time

Master mode

th(SI)

Slave mode

3.5

ta(SO

Data output access time

Slave mode

tdis(SO)

Data output disable time

Slave mode

tv(SO)

Data output valid time

Slave mode

1.65 V<VDD<3.6 V

-18

Slave mode

2.7 V<VDD<3.6 V

-18

tv(MO)

Master mode

th(SO)

Data output hold time

Slave mode

th(MO)

Master mode

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