IR35201MTYPBF datasheet(45/60 Pages) IRF

45 / 60 page

8+0/7+1/6+2 Dual Output Digital Multi-Phase Controller

IR35201

February 8, 2015 | V1.6

PSI[x]_L and TFN

PSI0_L is Power State Indicator Level 0. When this bit

is asserted the IR35201 will drop to 1 phase

depending on configuration. This will only occur if the

output current is low enough (typically <20A) to enter

PSI0, else the VR will remain in full phase operation.

PSI1_L is Power State Indicator Level 1. When this bit

is asserted along with the PSI0_L bit, the IR35201 will

enter diode emulation mode. This will only occur if the

output current is low enough (typically <5A) to enter

PSI1, else the VR will enter PSI0_L mode of

operation.

TFN is an active high signal that allows the processor

to control the telemetry functionality of the VR. If

TFN=1, then the VR telemetry will be configured per

Table 55.

TABLE 55: TFN TRUTH TABLE

VDD, VDDNB Domain

Selector bit

Meaning

0, 0

Telemetry is in voltage only mode.

0, 1

Telemetry is in voltage

& current mode.

1, 0

Telemetry is disabled.

1, 1

Reserved.

SVT Telemetry

The IR35201 has the ability to sample and report

voltage and current for the VDD and VDDNB

domains. The IR35201 reports this telemetry serially

over the SVT wire which is clocked by the processor

driven SVC. If in voltage-only telemetry mode then the

sampled voltage for VDD and VDDNB are sent

together in every SVT telemetry packet at a rate of

20kHz. If in voltage and current mode then the

sampled voltage and current for VDD is sent out in

one SVT telemetry packet followed by the sampled

voltage and current for VDDNB in the next SVT

telemetry packet at a rate of 40kHz. The voltage and

current are moving averages based on the filters and

update rates specified in the Electrical Specification

Table. The voltage is reported as a function of the Set

VID minus Iout times the Load Line Resistance. The

current is reported as a percentage of the Icc_max

00h represents 0% of the Icc_max setting. Resolution

of the current reporting is 0.39% (1/256).

Load Line Slope Trim

The IR35201 has the ability for the processor to

change the load line slope of each loop independently

through the SVI2 bus while ENABLE and PWROK are

asserted via the serial VID interface. The slope

change applies to initial load line slope as set by the

external RCSP/RCSM resistor network. The load line

slope can be disabled or adjusted by -40%, -20%, 0%,

+20%, +40%, +60%, or +80%.

Offset Trim

The IR35201 has the ability for the processor to

change the offset of each loop independently while

ENABLE and PWROK are asserted via the serial VID

interface. The offset can be left unchanged, disabled,

or changed +25mV or -25mV.

Ispike/Dual OCP Support

The IR35201 has two current limit thresholds. One

threshold is for short duration current spikes (Fast

OCP). When this threshold, typically a percentage

above the peak processor current, is exceeded, the

VR quickly shuts down. The other threshold, typically

a percentage above the thermal design current (TDC),

is heavily filtered (Slow OCP) and shuts down the VR

when the average current exceeds it. To meet AMD

specifications, exceeding both thresholds will assert

the OCP_L (VR_HOT) pin and delay the over-current

shut down by 10usec for FAST threshold and 20usec

for the SLOW threshold, typically. Figure 50 and

Figure 51 show the delay action of the OCP shutdown

with the OCP_L (VR_HOT) and PWRGD pins.

Figure 50: OCP_L (VR_HOT) assertion with

OCP_spike (Fast) threshold. OCP delay action (11usec)

OCP Delay

(fast)

Over-current

detected

VR shuts

down

Vdd

Idd

OCP_L

IR35201MTYPBF Datasheet(PDF) 45 Page - International Rectifier

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