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LAN8740Ai-EN Datasheet(PDF) 51 Page - Microchip Technology |
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LAN8740Ai-EN Datasheet(HTML) 51 Page - Microchip Technology |
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51 / 136 page  2013-2015 Microchip Technology Inc. DS00001987A-page 51 LAN8740A/LAN8740Ai 3.8.12 LOOPBACK OPERATION The device may be configured for near-end loopback and far loopback. These loopback modes are detailed in the fol- lowing subsections. 3.8.12.1 Near-end Loopback Near-end loopback mode sends the digital transmit data back out the receive data signals for testing purposes, as indi- cated by the blue arrows in Figure 3-14. The near-end loopback mode is enabled by setting the Loopback bit of the Basic Control Register to “1”. A large percentage of the digital circuitry is operational in near-end loopback mode because data is routed through the PCS and PMA layers into the PMD sublayer before it is looped back. The COL signal will be inactive in this mode, unless Collision Test is enabled in the Basic Control Register. The transmitters are powered down regardless of the state of TXEN. Refer to Section 5.6.3.1, "100 Mbps Internal Loopback MII Timing" for additional loopback timing information. 3.8.12.2 Far Loopback Far loopback is a special test mode for MDI (analog) loopback as indicated by the blue arrows in Figure 3-15. The far loopback mode is enabled by setting the FARLOOPBACK bit of the Mode Control/Status Register to “1”. In this mode, data that is received from the link partner on the MDI is looped back out to the link partner. The digital interface signals on the local MAC interface are isolated. FIGURE 3-14: NEAR-END LOOPBACK BLOCK DIAGRAM Note: This special test mode is only available when operating in RMII mode. FIGURE 3-15: FAR LOOPBACK BLOCK DIAGRAM Microchip Ethernet Transceiver 10/100 Ethernet MAC CAT-5 XFMR Digital RXD TXD Analog RX TX X X Far-end system Microchip Ethernet Transceiver 10/100 Ethernet MAC CAT-5 XFMR Digital RXD TXD Analog RX TX Link Partner X X |
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