LAN8700 datasheet(19/74 Pages) MICROCHIP

19 / 74 page

 2007-2016 Microchip Technology Inc.

DS00002260A-page 19

LAN8700/LAN8700i

For RMII, TXD[1:0] shall transition synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are

accepted for transmission by the LAN8700/LAN8700i. TXD[1:0] shall be “00” to indicate idle when TX_EN is deasserted.

Values of TXD[1:0] other than “00” when TX_EN is deasserted are reserved for out-of-band signalling (to be defined).

Values other than “00” on TXD[1:0] while TX_EN is deasserted shall be ignored by the LAN8700/LAN8700i.TXD[1:0]

shall provide valid data for each REF_CLK period while TX_EN is asserted.

4.4.2

MANCHESTER ENCODING

The 4-bit wide data is sent to the TX10M block. The nibbles are converted to a 10Mbps serial NRZI data stream. The

10M PLL locks onto the external clock or internal oscillator and produces a 20MHz clock. This is used to Manchester

encode the NRZ data stream. When no data is being transmitted (TX_EN is low), the TX10M block outputs Normal Link

Pulses (NLPs) to maintain communications with the remote link partner.

4.4.3

10M TRANSMIT DRIVERS

The Manchester encoded data is sent to the analog transmitter where it is shaped and filtered before being driven out

as a differential signal across the TXP and TXN outputs.

4.5

10Base-T Receive

The 10Base-T receiver gets the Manchester- encoded analog signal from the cable via the magnetics. It recovers the

receive clock from the signal and uses this clock to recover the NRZI data stream. This 10M serial data is converted to

4-bit data nibbles which are passed to the controller across the MII at a rate of 2.5MHz.

This 10M receiver uses the following blocks:

• Filter and SQUELCH (analog)

• 10M PLL (analog)

• RX 10M (digital)

• MII (digital)

4.5.1

10M RECEIVE INPUT AND SQUELCH

The Manchester signal from the cable is fed into the PHY (on inputs RXP and RXN) via 1:1 ratio magnetics. It is first

filtered to reduce any out-of-band noise. It then passes through a SQUELCH circuit. The SQUELCH is a set of amplitude

and timing comparators that normally reject differential voltage levels below 300mV and detect and recognize differential

voltages above 585mV.

4.5.2

MANCHESTER DECODING

The output of the SQUELCH goes to the RX10M block where it is validated as Manchester encoded data. The polarity

of the signal is also checked. If the polarity is reversed (local RXP is connected to RXN of the remote partner and vice

versa), then this is identified and corrected. The reversed condition is indicated by the flag “XPOL“, bit 4 in register 27.

The 10M PLL is locked onto the received Manchester signal and from this, generates the received 20MHz clock. Using

this clock, the Manchester encoded data is extracted and converted to a 10MHz NRZI data stream. It is then converted

from serial to 4-bit wide parallel data.

The RX10M block also detects valid 10Base-T IDLE signals - Normal Link Pulses (NLPs) - to maintain the link.

4.5.3

10M RECEIVE DATA ACROSS THE MII/RMII INTERFACE

For MII, the 4 bit data nibbles are sent to the MII block. In MII mode, these data nibbles are valid on the rising edge of

the 2.5 MHz RX_CLK.

For RMII, the 2bit data nibbles are sent to the RMII block. In RMII mode, these data nibbles are valid on the rising edge

of the RMII REF_CLK.

4.5.4

JABBER DETECTION

Jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length,

usually due to a fault condition, that results in holding the TX_EN input for a long period. Special logic is used to detect

the jabber state and abort the transmission to the line, within 45ms. Once TX_EN is deasserted, the logic resets the

jabber condition.

As shown in Table 5-31, bit 1.1 indicates that a jabber condition was detected.

LAN8700 Datasheet(PDF) 19 Page - Microchip Technology

LAN8700 Datasheet(HTML) 19 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

Datasheet Download

Link URL