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TDP158 Datasheet(PDF) 24 Page - Texas Instruments

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Part # TDP158
Description  6-Gbps, AC-Coupled to TMDS or HDMI Redriver
PDF  55 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TDP158 Datasheet(HTML) 24 Page - Texas Instruments

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TDP158
SLLSEX2 – DECEMBER 2016
www.ti.com
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Feature Description (continued)
Table 1. Power Up and Operation Timing Requirements
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
td1
VCC stable before Vdd
0
200
µs
td1
VDD and VCC stable before OE de-assertion
100
µs
VDD(ramp)
VDD supply ramp up requirements
0.2
100
ms
VCC(ramp)
VCC supply ramp up requirements
0.2
100
ms
8.3.3 Lane Control
The TDP158 has various lane control features. By default the high speed lanes are globally controlled. Pin
strapping can globally control features like receiver equalization, VOD swing and Pre-emphasis. I
2C programming
performs the same global programming using default configurations. Through I2C a method to control receive
equalization, transmitter swing (VOD) and Pre-emphasis on each individual lane. Setting reg09h[5] = 1 puts the
device into independent lane configuration mode.
Reg31h[7:3] controls the clock lane, reg32h[7:3] controls lane D0, reg33h[7:3] controls lane D1 and reg34h[7:3]
controls lane D2 while Reg4E and Reg4F control the individual lane EQ control.
NOTE
If the swap function is enabled and individual lane control has been implemented it is
recommended to reprogram the lanes to make sure they match the expected results.
Register are mapped to the pin name convention.
8.3.4 Swap
TDP158 incorporates a swap function which can swap the lanes, see Figure 23. The EQ, Pre-emphasis,
termination, and slew setup will follow the new mapping. This function can be used with the SCL_CTL/SWAP pin
13 when I2C_EN pin 8 is low or can be implemented using control the register 0x09h bit 7 and is only valid for
HDMI Mode.
Table 2. TBD
Normal Operation
SWAP = L or CSR 0x09h bit 7 is 1’b1
IN_D2
→ OUT_D2
IN_CLK
→ OUT_CLK
IN_D1
→ OUT_D1
IN_D0
→ OUT_D0
IN_D0
→ OUT_D0
IN_D1
→ OUT_D1
IN_CLK
→ OUT_CLK
IN_CLK
→ OUT_CLK



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