LAN9250 datasheet(165/421 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001913A-page 165

LAN9250

11.11.5

CALCULATING ACTUAL TX DATA FIFO USAGE

The following rules are used to calculate the actual TX Data FIFO space consumed by a TX Packet:

• TX command 'A' is stored in the TX Data FIFO for every TX buffer

• TX command 'B' is written into the TX Data FIFO when the First Segment (FS) bit is set in TX command 'A'

• Any DWORD-long data added as part of the “Data Start Offset” is removed from each buffer before the data is

written to the TX Data FIFO. Any data that is less than 1 DWORD is passed to the TX Data FIFO.

• Payload from each buffer within a Packet is written into the TX Data FIFO.

• Any DWORD-long data added as part of the End Padding is removed from each buffer before the data is written to

the TX Data FIFO. Any end padding that is less than 1 DWORD is passed to the TX Data FIFO

11.11.6

TRANSMIT EXAMPLES

11.11.6.1

TX Example 1

In this example a single, 111-Byte Ethernet packet will be transmitted. This packet is divided into three buffers. The three

buffers are as follows:

Buffer 0:

• 7-Byte “Data Start Offset”

• 79-Bytes of payload data

• 16-Byte “Buffer End Alignment”

Buffer 1:

• 0-Byte “Data Start Offset”

• 15-Bytes of payload data

• 16-Byte “Buffer End Alignment”

Buffer 2:

• 10-Byte “Data Start Offset”

• 17-Bytes of payload data

• 16-Byte “Buffer End Alignment”

Excessive Deferral.

If the deferred bit is set in the control register, the setting of the excessive deferral

bit indicates that the transmission has ended because of a deferral of over 24288 bit times during trans-

mission.

Reserved.

This bit is reserved.

Deferred.

When set, this bit indicates that the current packet transmission was deferred.

Bits

Description

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