MCP6V71 datasheet(19/46 Pages) MICROCHIP

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DS20005385B-page 19

MCP6V71/1U/2/4

4.1.3

INTERMODULATION DISTORTION

(IMD)

These op amps will show intermodulation distortion

(IMD) products when an AC signal is present.

The signal and clock can be decomposed into sine

wave tones (Fourier series components). These tones

interact with the zero-drift circuitry’s nonlinear response

to produce IMD tones at sum and difference frequen-

cies. Each of the square wave clock’s harmonics has a

series of IMD tones centered on it. See Figures 2-40

and 2-41.

4.2

Other Functional Blocks

4.2.1

RAIL-TO-RAIL INPUTS

The input stage of the MCP6V71/1U/2/4 op amps uses

two differential CMOS input stages in parallel. One

operates at low Common Mode Input Voltage (VCM,

which is approximately equal to VIN+ and VIN- in normal

operation) and the other at high VCM. With this

topology, the input operates with VCM up to VDD +0.3V,

and down to VSS – 0.2V, at +25°C (see Figure 2-19).

The input offset voltage (VOS) is measured at

VCM =VSS – 0.2V and VDD + 0.3V to ensure proper

operation.

4.2.1.1

Phase Reversal

The input devices are designed to not exhibit phase

inversion when the input pins exceed the supply

voltages.

Figure 2-46 shows

input voltage

exceeding both supplies with no phase inversion.

4.2.1.2

Input Voltage Limits

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the voltages at

the input pins (see Section 1.1 “Absolute Maximum

Ratings †”

). This requirement is independent of the

current limits discussed later.

The ESD protection on the inputs can be depicted as

shown in Figure 4-4. This structure was chosen to

protect the input transistors against many (but not all)

overvoltage conditions and to minimize input bias

current (IB).

FIGURE 4-4:

Simplified Analog Input ESD

Structures.

The input ESD diodes clamp the inputs when they try

to go more than one diode drop below VSS. They also

clamp any voltages well above VDD; their breakdown

voltage is high enough to allow normal operation, but

not low enough to protect against slow overvoltage

(beyond VDD) events. Very fast ESD events (that meet

the spec) are limited so that damage does not occur.

In some applications, it may be necessary to prevent

excessive voltages from reaching the op amp inputs;

Figure 4-5 shows one approach to protecting these

inputs. D1 and D2 may be small signal silicon diodes,

Schottky diodes for lower clamping voltages or diode-

connected FETs for low leakage.

FIGURE 4-5:

Protecting the Analog Inputs

Against High Voltages.

Bond

Pad

Bond

Pad

Bond

Pad

VDD

VIN+

VSS

Input

Stage

Bond

Pad

VIN–

VDD

VOUT

MCP6V7X

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